slaclab / surf

A huge VHDL library for FPGA development
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Create SaciAxiLiteMaster module #1163

Closed bengineerd closed 2 months ago

bengineerd commented 5 months ago

Description

Add a new SaciAxiLiteMaster module. This module is intended to be paired with AxiLiteSaciMaster. Together they create a an AXI-Lite bridge between two chips carried over the SACI bus.

Details

Only 20 bits of AXI-Lite address space are available, due to the limited address bits on the SACI bus protocol.

Also added a cocotb testbench for the new module.