issues
search
slaclab
/
surf
A huge VHDL library for FPGA development
Other
346
stars
55
forks
source link
Update DmaXvcWrapper.vhd
#1177
Closed
ruck314
closed
4 months ago
ruck314
commented
4 months ago
Description
AXIS_CLK_FREQ_G is misleading name because generic is associated with the xvcClk (not axisClk) at surf.UdpDebugBridgeWrapper
Renaming this generic to XVC_CLK_FREQ_G
VALID_THOLD_G => 0, -- 0 = only when frame ready
is required to fix the issue when there are tValid gaps in the transfer
https://jira.slac.stanford.edu/browse/ESROGUE-671
Description
VALID_THOLD_G => 0, -- 0 = only when frame ready
is required to fix the issue when there are tValid gaps in the transfer