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slaclab / surf

A huge VHDL library for FPGA development
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AxiVersion.py Update #1180

Closed ruck314 closed 1 week ago

ruck314 commented 1 month ago

Description

ruck314 commented 1 month ago

@bengineerd What would you recommend doing instead?

bengineerd commented 1 month ago

There's probably a way to detect the first read of the register and check it then. I need to think about how that would work. It's up to you whether to merge this now or wait for that fix.