Release [2021.1.1]

[paulmnt]

[2021.1.1]

Added

• Ibex
  • Enable ESP cache hierarchy with Ibex core (#92)

Fixed

• Cache hierarchy

  • Fix endianness of the SystemC implementation for instances of ESP using a RISC-V core (#92)

• Ibex

  • Use Xilinx primitives for Ibex implementation on FPGA
  • Disable ESP L2 invalidation master port on AHB bus (#92)

• Infrastructure

  • Fix link update of the object dump used in full-system RTL simulations (#93)
  • Save HLS log files for the cache hierarchy into log folder
  • Restore optimized floorplanning for proFPGA XCVU440 (#94)