Describe the bug
A recent commit moved the creation of the symbolic links to ram.srec and prom.srec to the targets xmsim-compile and ncsim-compile. This allows users to switch between processor cores without cleaning the simulation folder. However, it appears that while xmelab and ncelab were importing those links, because they existed at elaboration time, xmupdate and ncupdate do not.
To Reproduce
From a clean soc folder run xmsim or ncsim targets
Expected behavior
A simple fix to the make targets is needed to create those links in the work folders of Xcelium and Incisive: xcelium/work and incisive/work.
paulmnt
commented
3 years ago
Describe the bug A recent commit moved the creation of the symbolic links to ram.srec and prom.srec to the targets xmsim-compile and ncsim-compile. This allows users to switch between processor cores without cleaning the simulation folder. However, it appears that while xmelab and ncelab were importing those links, because they existed at elaboration time, xmupdate and ncupdate do not.
To Reproduce From a clean soc folder run xmsim or ncsim targets
Expected behavior A simple fix to the make targets is needed to create those links in the
workfolders of Xcelium and Incisive:xcelium/workandincisive/work.