New architecture features

[paulmnt]

New

• add optional DDR interface for SLM tile from Basejump STL [Taylor, DAC'18]
• add preliminary support for Spandex caches [Alsop et. al, ISCA'18] (FPGA implementation needs to improve to meet timing)
• add design example for ASIC (requires separate access to GF12 technology)
  • template design for ASIC
  • digital clock oscillator wrapper
  • SRAM and pads wrappers
  • per-tile PADs configuration pass through
  • FPGA proxy design for main-memory access
  • JTAG trace-based simulation for single-tile debug
  • support for SDF back-annotation of user-selected IPs
• add support for RISC-V atomics to the cache hierarchy
• increase hardware maximum number of interrupt lines from 16 to 256

Fix

• fix NoC header parsing in LLC wrapper (#103)
• fix HLS scripts for ESP caches in SystemC
• support Stratus 20.24 across all components in SystemC
• support Xcelium 19.03 for simulation of ESP and SystemC components in unit test mode