Add support to ESP for creating and integrating an accelerator designed in Verilog, SystemVerilog or VHDL.
This RTL accelerator design flow is a preliminary version. Like other accelerator design flow in ESP, it includes the automated integration of the accelerator and the generation of Linux device driver and skeletons of the bare-metal and Linux test applications. However, it generates an empty top module of the accelerator, and the job of implementing the accelerator is left to the designer.
Add support to ESP for creating and integrating an accelerator designed in Verilog, SystemVerilog or VHDL.
This RTL accelerator design flow is a preliminary version. Like other accelerator design flow in ESP, it includes the automated integration of the accelerator and the generation of Linux device driver and skeletons of the bare-metal and Linux test applications. However, it generates an empty top module of the accelerator, and the job of implementing the accelerator is left to the designer.
Here is the tutorial guide for this design flow.