Support for booting Linux SMP with up to 4 RISC-V Ariane processors:
-Added dcache-inval unit in Ariane processor to receive invalidations from ESP L2 over an ACE bus
-Patch Linux to mitigate RCU stall issue
-Switch from the riscv-pk to openSBI
-Updates to SystemC and SystemVerilog caches to support RISC-V multicore while maintaining backwards compatibility
Support for booting Linux SMP with up to 4 RISC-V Ariane processors: -Added dcache-inval unit in Ariane processor to receive invalidations from ESP L2 over an ACE bus -Patch Linux to mitigate RCU stall issue -Switch from the riscv-pk to openSBI -Updates to SystemC and SystemVerilog caches to support RISC-V multicore while maintaining backwards compatibility