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Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
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Issues while doing synthesis of single core #147

Closed mayank-kabra2001 closed 2 years ago

mayank-kabra2001 commented 2 years ago

I checked out the following issue (https://github.com/sld-columbia/esp/issues/67) and updated my system to 12 cores and 12 gb ram with 10 cores and 10 gb allocated to VM where I am running esp, but still error is coming.

mig_synth_1: /home/centos/esp/socs/xilinx-vc707-xc7vx485t/vivado/esp-xilinx-vc707-xc7vx485t.runs/mig_synth_1/runme.log sgmii_synth_1: /home/centos/esp/socs/xilinx-vc707-xc7vx485t/vivado/esp-xilinx-vc707-xc7vx485t.runs/sgmii_synth_1/runme.log [Wed Feb 16 19:53:49 2022] Launched synth_1... Run output will be captured here: /home/centos/esp/socs/xilinx-vc707-xc7vx485t/vivado/esp-xilinx-vc707-xc7vx485t.runs/synth_1/runme.log launch_runs: Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 1692.918 ; gain = 31.387 ; free physical = 5251 ; free virtual = 11488 [Wed Feb 16 19:53:49 2022] Waiting for synth_1 to finish (timeout in 360 minutes)... [Wed Feb 16 19:54:28 2022] synth_1 finished WARNING: [Vivado 12-8222] Failed run(s) : 'mig_synth_1', 'sgmii_synth_1' wait_on_run: Time (s): cpu = 00:00:28 ; elapsed = 00:00:39 . Memory (MB): peak = 1692.918 ; gain = 0.000 ; free physical = 5305 ; free virtual = 11541 ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s): mig_synth_1 sgmii_synth_1 These failed run(s) need to be reset prior to launching 'impl_1' again.

ERROR: bistream not found; synthesis failed

I have attached runme.log , vivado.log , syn.tcl , esp_env_cad.sh

syn.tcl -> open_project esp-xilinx-vc707-xc7vx485t.xpr update_ip_catalog update_compile_order -fileset sources_1 reset_run impl_1 reset_run synth_1 launch_runs synth_1 -jobs 2 get_ips wait_on_run -timeout 360 synth_1 set_msg_config -suppress -id {Drc 23-20} launch_runs impl_1 -jobs 2 wait_on_run -timeout 360 impl_1 launch_runs impl_1 -to_step write_bitstream wait_on_run -timeout 60 impl_1

mig_synth_1 -> runme.log

sgmii_synth_1 -> not generated

Vivado log -> vivado.log

esp_cad_env.sh ->

Cadence: Stratus HLS, Incisive, Xcelium

e.g. = /opt/cadence/stratus2024

e.g. = /opt/cadence/incisive152

e.g. = /opt/cadence/xcelium1903

export LM_LICENSE_FILE=$LM_LICENSE_FILE:5279@172.16.201.225

export PATH=$PATH:/bin:

De-comment either Incisive or Xcelium paths, but not both!

export PATH=$PATH:/tools/cdsgcc/gcc/bin

export PATH=$PATH:/tools/bin

export PATH=$PATH:/mnt/cadence_tools/XCELIUM/tools/cdsgcc/gcc/bin export PATH=$PATH:/mnt/cadence_tools/XCELIUM/tools/bin export CDS_AUTO_64BIT=all

export HOST=$(hostname) # for Ubuntu only

Xilinx: Vivado, Vivado HLS

e.g. = /opt/xilinx/Vivado/2019.2

export XILINXD_LICENSE_FILE=/home/centos/Xilinx.lic source /home/digital2/Vivado/Vivado/2019.2/settings64.sh

Mentor: Catapult HLS, Modelsim

e.g. = /opt/mentor/modeltech

e.g. = /opt/mentor/catapult

export LM_LICENSE_FILE=$LM_LICENSE_FILE:

export PATH=$PATH:/bin

export AMS_MODEL_TECH=

export PATH=$PATH:/Mgc_home/bin

export SYSTEMC=/Mgc_home/shared

export SYSTEMC_HOME=/Mgc_home/shared

export MGC_HOME=/Mgc_home

export LIBDIR=-L/Mgc_home/shared/lib $LIBDIR

RISC-V (for Ariane and Ibex)

e.g. = /opt/riscv

e.g. = /opt/riscv32imc

export RISCV=/opt/riscv export RISCV32IMC=/opt/riscv32imc export PATH=$PATH:/opt/riscv/bin:/opt/riscv32imc/bin

Leon3

e.g. = /opt/leon

export PATH=$PATH:/opt/leon/bin export PATH=$PATH:/opt/leon/mklinuximg export PATH=$PATH:/opt/leon/sparc-elf/bin

jzuckerman commented 2 years ago

From the log for the mig_synth, it seems like Vivado can't find a valid license on your machine.

mayank-kabra2001 commented 2 years ago

I have my license at path /home/centos/Xilinx.lic and I have kept it same as in the environment variable script as shown above.

jzuckerman commented 2 years ago

The log suggests running the Vivado License Manager to see what features you have access to. If you run this manager, what does it tell you?

mayank-kabra2001 commented 2 years ago

image

jzuckerman commented 2 years ago

It looks like for Syntheses the Host ID does not match. I'm not 100% sure what this means, but it looks like a problem with the license that won't allow synthesis until it's fixed.

SaltedFishLZ commented 1 year ago

Same here. My problem comes with sgmii_synth_1

Do we need to buy a MIG license? https://www.xilinx.com/products/intellectual-property/mig.html#overview I am using the academic license provided by my university but it looks like it doesn't contain any IP license.

It looks like the IP that comes with Vivado 2020 is outdated. I opened the project (.xpr file) with GUI and found that. After updating the IP, I can synthesize the design.