Error while doing "make vivado-syn" for single-core Ariane SoC on Xilinx VCU128

[ankurlimaye2]

I am trying to follow the steps mentioned in How to: design a single-core SoC for the default single-core Ariane SoC with ESP RTL caches on Xilinx VCU128 FPGA board. However, when running the "make vivado-syn", synthesis fails (Error: Failed synthesizing module 'llc_localmem_gf12')

Here's the attached Vivado synthesis log: vivado_syn.log

Desktop (please complete the following information):

• OS: Ubuntu 18.04.6 LTS
• CAD tools versions: Xilinx Vivado 2020.2

[jzuckerman]

ESP officially supports Vivado 2019.2. Can you try again with that version of the tool?

[ankurlimaye2]

Using 2019.2 resolved the issue. Thank you!