Fixes to SLM+DDR tile - Githubissues

sld-columbia / esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

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Fixes to SLM+DDR tile #169

Closed jzuckerman closed 2 years ago

jzuckerman commented 2 years ago

-use correct clocks in asic_tile_slm_ddr -add configurable delay cells on dco outputs in tile_slm -fix ahb2bsg_dmc to support accelerator execution to slm_ddr tile -modify delay cell configuration from CSRs