Vivado HLS failed to package/export IP due to Xilinx's bug

[SaltedFishLZ]

Describe the bug When I tried to Vivado HLS tutorial to generate the MAC accelerator, Vivado HLS cannot package and export the IP due to a known bug from Xilinx.

Check the following links: https://support.xilinx.com/s/question/0D52E00006uxPZBSA2/detail https://support.xilinx.com/s/question/0D52E00006uxy49SAA/vivado-fails-to-export-ips-with-the-error-message-bad-lexical-cast-source-type-value-could-not-be-interpreted-as-target?language=en_US

To Reproduce Steps to reproduce the behavior: Follow the tutorial on Vivado HLS accelerator.

Expected behavior The csim and syn parts are OK. But Vivado HLS cannot export IP and will report the following error: bad lexical cast: source type value could not be interpreted as target while executing "rdi::set_property core_revision

It is due to a bug by Xilinx that uses the timestamp to identify each packaged HLS IP. The code uses a 32-bit int to store the timestamp and 22MMDDHHMM will cause an overflow.

Desktop (please complete the following information):

• OS: Docker Image: esp-centos7-full
• CAD tools versions: Xilinx Vivado 2019.2

Temporary Workaround

Change my system time back to 2020 when exporting HLS IP. Needs to update the instructions in the tutorial.

[jzuckerman]

We've used the following patch from Xilinx to resolve this issue: https://support.xilinx.com/s/article/76960?language=en_US

[SaltedFishLZ]

Thanks.