Closed paulmnt closed 4 years ago
Commit a1a97a9bb0bd8b29efa75e7e61389ebe18622c80 forces Make to exit if Xilinx libraries compilation fails and removes the target's folder. This way a new execution of the simulation target will first attempt to compile Xilinx libraries again. Upon failure, a new error message is printed to let the user know that the Simulator, or Vivado, could not compile the libraries.
This commit fixes inclusions of ProFPGA files for users who don't have access to the ProFPGA RTL release.
make sim
, before setting CAD tools environment requires amake sim-distclean
to enable correct compilation.