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Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
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Improve synthetic app and accelerator, improve libesp, various cache fixes
#49
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jzuckerman
closed
4 years ago
jzuckerman
commented
4 years ago
improve synthetic application, accelerator, and libesp API
enable more than 2 memory tiles in contig_alloc
floorplanning constraints for 2MB LLC
bux fixes in caches and cache-wrapper
pipeline monitor signals on profpga-xcvu440