From the ESP GUI it is now possible to generate an SoC map without memory tiles, if the selected processor core is the lowRISC ibex and there is at least one shared-local memory (SLM) tile.
The SLM tile consists of a software-managed scratchpad memory that can support non-coherent accesses from processor cores, as well as from accelerators.
When selecting the ibex core, an ESP system can be generated without memory tiles. In this case, the memory in the SLM tiles is mapped as a contiguous region starting at the address of main memory. A bare metal program can therefore execute leveraging the on-chip memory, as long as its footprint is smaller than the total capacity of the SLM tiles.
From the ESP GUI it is now possible to generate an SoC map without memory tiles, if the selected processor core is the lowRISC ibex and there is at least one shared-local memory (SLM) tile.
The SLM tile consists of a software-managed scratchpad memory that can support non-coherent accesses from processor cores, as well as from accelerators. When selecting the ibex core, an ESP system can be generated without memory tiles. In this case, the memory in the SLM tiles is mapped as a contiguous region starting at the address of main memory. A bare metal program can therefore execute leveraging the on-chip memory, as long as its footprint is smaller than the total capacity of the SLM tiles.