Device drivers, including bare metal applications, should be able to probe the hardware and detect whether the ESP cache hierarchy is present and whether the accelerator has the private L2 cache in the tile.
After probe, this information should be stored in the device data structure and used to prevent invocations with coherence models not enabled in the current hardware configuration.
Device drivers, including bare metal applications, should be able to probe the hardware and detect whether the ESP cache hierarchy is present and whether the accelerator has the private L2 cache in the tile.
After probe, this information should be stored in the device data structure and used to prevent invocations with coherence models not enabled in the current hardware configuration.