This PR adds ESP design templates for Xilinx Evaluation Board ZCU102 and ZCU106.
Both designs are intended to use a 1GB memory region allocated in the PS-side DDR of the ZYNQ MP SoC.
The designs support only one memory tile, which is connected to one high-performance coherent AXI port of the PS.
The memory bridge leverages the Xilinx AHB-L-to-AXI adapter and has a data width of 32 or 64 bits, based on the ESP configuration.
The ESP instance on the PL has no direct access to Ethernet, hence the debug interface is tethered to one of the AXI
master ports of the PS through the Xilinx AXI-to-AHB-L adapter.
The ESP UART interface is directly connected from the PL to the second channel of the CP210x Quad UART-to-USB chip available on both ZCU102 and ZCU106.
This PR includes the integration of the ZYNQ Linux flow to automatically boot the host system on and deploy ESP on the PL
The support for ZYNQ MP SoC based boards is still missing the following components:
Automated patch of the ZYNQ device tree: define the 1GB memory region reserved to ESP
ESPLink for ZYNQ: replace Ethernet-based communication with I/O memory area remap to user-space
CREDITS: thanks to #JuanEsco063 for contributing the design templates for ZYNQ MP SoC based boards.
This PR adds ESP design templates for Xilinx Evaluation Board ZCU102 and ZCU106.
This PR includes the integration of the ZYNQ Linux flow to automatically boot the host system on and deploy ESP on the PL
The support for ZYNQ MP SoC based boards is still missing the following components:
CREDITS: thanks to #JuanEsco063 for contributing the design templates for ZYNQ MP SoC based boards.