Consolidating and cleaning up RTL, automation tools and software

[paulmnt]

This PR applies a major restructuring to the ESP repository. File names and locations have changed to obtain a better organization of the RTL source files, of the ESP automation tools and of the software stack.

RTL

• RTL folders are now organized based on the ESP architecture
• The new names of the key components of the ESP sockets convey their main function
• Third-party IPs are integrated as part of the architecture hierarchy
• Unused files from GRLIB have been removed
• GRLIB technology-specific files only include component mappings for technologies supported by ESP
• The folder esp/tech now contains only files generated through the HLS flows

• Non-generated files previously stored in esp/tech are now included in the rtl/techmap folder

  Tools

  • The new esp/tools folder contains all the ESP scripts and automation tools for accelerators design and SoC integration
  • Tools have been renamed to better convey their function

  Accelerators

  • All accelerator flows, including chisel and third-party are nested under the esp/accelerators folder
  • Third-party accelerators include a new .host file to indicate which processor core supports their execution
  • Accelerators examples have a consistent naming across all flows
  • Accelerators examples folders have a consistent structure across all flows

  Software

  • All software is built inside the ESP working design folder.
  • Software binaries are built in a specific folder for each core, thus users can switch core in the ESP SoCGen GUI without having to clean the design folder.
  • The ESP baremetal and Linux common library folders are not replicated in each processor software support folder
  • The device drivers, Linux applications and bare metal drivers source files are stored in the accelerators' design folders.

  Minor bug fixes and features improvements

  • Use https URL for Zynq submodule
  • Fix Genus elaboration error due to AXI control wires padding for third-party flow
  • Add support for Mentor Questasim
  • Fix Xilinx library compilation for Xcelium (Xcelium 19.03 may not support simulation of some accelerators designed with Vivado HLS 2019.2)
  • Clear compilation warnings in Leon3 bare metal applications