D1s DRAM `mctl_phy_ac_remapping()` issue

[YuzukiTsuru]

in mctl_phy_ac_remapping we got

if (para->dram_type == 2) {
    if (fuse == 15) return; 
    memcpy_self(cfg0, cfg6, 22);

but for d1s there is no remap needed due to sip ddr2 chip, with this code will get an error

DX0 state: 3
DX1 state: 3
ERROR: auto scan dram rank & width failed
auto_scan_dram_config() FAILED

so I add this and it pass the test

if (fuse == 0x0a) {
  sys_uart_printf("D1s no REMAP!!\r\n");
  return;
}

DRAM CLK     -> 528
DRAM TYPE    -> 2
DRAM ZQ      -> 7b7bf9
Start Init DRAM...
DRAM BOOT DRIVE INFO: %s
DRAM CLK = 528 MHz
DRAM Type = 2 (2:DDR2,3:DDR3)
DRAMC read ODT off
ZQ value = 0x2f
DDR CLK = 1056 MHz
DDR efuse: 0xa
D1s no REMAP!!
single rank and full DQ!
DDR CLK = 1056 MHz
DDR efuse: 0xa
D1s no REMAP!!
rank 0 row = 16
rank 0 bank = 8
rank 0 page size = 8 KB
DRAM ODT off
DDR CLK = 1056 MHz
DDR efuse: 0xa
D1s no REMAP!!
DRAM: size = 4096MB
DRAM: simple test FAIL
fedcc098 != 1234567 at address %p

but as you see the dram size is wrong. so there were some where got an error.

BTW, here is my test driver for d1s: https://github.com/YuzukiHD/TinyKasKit/blob/master/d1s-dramc/src/sys/sys-dram.c, I add some comment and reg list for it.

[YuzukiTsuru]

Test the asm driver and realize the rank and bank, row was wrong

ZQ value = 0x2f
get_pmu_exist() = 4294967295
ddr_efuse_type: 0xa
single rank and full DQ!
ddr_efuse_type: 0xa
rank 0 row = 13
rank 0 bank = 4
rank 0 page size = 2 KB
DRAM BOOT DRIVE INFO: Shipped
DRAM CLK = 528 MHz
DRAM Type = 2 (2:DDR2,3:DDR3)
DRAMC read ODT  off.
DRAM ODT off.
ddr_efuse_type: 0xa
DRAM SIZE = 64 M

[YuzukiTsuru]

OK I Fix it. soon will upload a new version of auto_scan_dram_size

[YuzukiTsuru]

Fixed. https://github.com/YuzukiHD/TinyKasKit/commit/1bc76937dcf3f7cac2d1e689a139927eb57d92d7

[smaeul]

Thank you very much for the explanation and the fixes! With your changes, I was able to get U-Boot's driver to support all three of D1, D1s, and T113. Here are the changes I made:

commit 9e4ebfe1ef4513e480ca7ca3f8a3075d9d9f0a3d
Author: Samuel Holland <samuel@sholland.org>
Date:   Sat Dec 9 11:40:40 2023 -0600

    ram: sun20i_d1: Disable AC remapping for D1s/F133

    D1s chips appear to be programmed with eFuse value 10, but
    AC remapping breaks DRAM init in auto_scan_dram_rank_width().

    Link: https://github.com/smaeul/sun20i_d1_spl/issues/14
    Link: https://github.com/YuzukiHD/TinyKasKit/commit/b598843d7b6a
    Reported-by: YuzukiTsuru <gloomyghost@gloomyghost.com>
    Signed-off-by: Samuel Holland <samuel@sholland.org>

diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c b/drivers/ram/sunxi/dram_sun20i_d1.c
index 38379281d73..a14a5152161 100644
--- a/drivers/ram/sunxi/dram_sun20i_d1.c
+++ b/drivers/ram/sunxi/dram_sun20i_d1.c
@@ -665,7 +665,7 @@ static void mctl_phy_ac_remapping(const dram_para_t *para,
        debug("DDR efuse: 0x%x\n", fuse);

        if (para->dram_type == SUNXI_DRAM_TYPE_DDR2) {
-               if (fuse == 15)
+               if (fuse == 10 || fuse == 15)
                        return;
                cfg = ac_remapping_tables[6];
        } else {

commit 67cde35cae06e4b04ac002c1b68b544bd89ccafb
Author: Samuel Holland <samuel@sholland.org>
Date:   Sat Dec 9 11:45:36 2023 -0600

    ram: sun20i_d1: Fix automatic bank detection

    The check is expected to pass on D1s, where the DRAM die has only one
    bank, as signified by bit 12 being unset in the stock dram_para1 value.
    Changing the offset matches the algorithm from dram_sunxi_dw.c (which
    uses 2 bank bits + 9 page bits), and works on D1, D1s, and T113-S3.

    Link: https://github.com/smaeul/sun20i_d1_spl/issues/14
    Link: https://github.com/YuzukiHD/TinyKasKit/commit/1bc76937dcf3
    Reported-by: YuzukiTsuru <gloomyghost@gloomyghost.com>
    Signed-off-by: Samuel Holland <samuel@sholland.org>

diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c b/drivers/ram/sunxi/dram_sun20i_d1.c
index a14a5152161..cd55513c350 100644
--- a/drivers/ram/sunxi/dram_sun20i_d1.c
+++ b/drivers/ram/sunxi/dram_sun20i_d1.c
@@ -1100,7 +1100,7 @@ static int auto_scan_dram_size(const dram_para_t *para, dram_config_t *config)
                udelay(1);

                // Test if bit A23 is BA2 or mirror XXX A22?
-               chk = CFG_SYS_SDRAM_BASE + (1U << 22);
+               chk = CFG_SYS_SDRAM_BASE + (1U << 11);
                ptr = CFG_SYS_SDRAM_BASE;
                for (i = 0, j = 0; i < 64; i++) {
                        if (readl(chk) != get_payload(i & 1, ptr)) {

With U-Boot SPL working, I'm not really maintaining this project anymore. I tried applying the same changes here, but they didn't immediately work, and I'm not interested in debugging it, so I'm just going to close this issue.