06/24/24

[badeaa3]

Goals:

• [ ] 1. merge Cristian's firmware branch into master and delete all auxiliary branches
• [x] 2. read from sw_read32_0 and sw_read32_1
• [x] 3. see the scanChain counter working on the scope -> discussed with Cristian see comment below

[badeaa3]

Goal 2: Pass

Successfully read from sw_read32_0 and sw_read32_1. I recloned the repo in a fresh directory, generated the bitstream, and flashed the fpga.

https://github.com/badeaa3/smartpix-lab-notebooks/assets/13281375/09b88835-3c07-40d0-97c0-8f2b570ea7c1

• fw_read_data32 gets assigned to sw_read32_0 https://github.com/SpacelyProject/spacely-caribou-common-blocks/blob/cg_cms_pix28_fw/cms_pix_28_test_firmware/src/fw_ip2.sv#L166
• fw_read_status32 gets assigned to sw_read32_0 How to interpret status codes inside of sw_read32_1: https://github.com/SpacelyProject/spacely-caribou-common-blocks/blob/cg_cms_pix28_fw/cms_pix_28_test_firmware/src/fw_ip2.sv#L168-L199
  • in status code we sent a write and read corresponding to these assigns https://github.com/SpacelyProject/spacely-caribou-common-blocks/blob/cg_cms_pix28_fw/cms_pix_28_test_firmware/src/fw_ip2.sv#L180-L181. This created a bit string 110 = 4+2+0 = 6. This is what we see in sw_read32_1 as the status code.

[badeaa3]

Goal 3: Pass

• Ran ROUTINE_scanChain_counter
• Set the scope trigger to single event and triggering on ScanIn pin 23
• Expected to see pulses of various widths based on the hex list sent

  hex_lists = [
  ["4'h2", "4'h2", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"], # write op code 2 (write)                                       
  ["4'h2", "4'h6", "8'h0", "16'h1"], # write op code 6 (array 0) writing to address 0 (8'h0) value 1 (16'h1)
  ["4'h2", "4'h6", "8'h1", "16'h3"], # write op code 6 (array 0) writing to address 1 (8'h1) value 3 (16'h3)
  ["4'h2", "4'h6", "8'h2", "16'h7"], # write op code 6 (array 0) writing to address 2 (8'h7) value 7 (16'h7)
  ["4'h2", "4'h6", "8'h3", "16'hf"], # write op code 6 (array 0) writing to address 3 (8'hf) value 2 (16'hf)
  ["4'h2", "4'h6", "8'h5", "16'hff"], # write op code 6 (array 0) writing to address 5 (8'hf) value 2 (16'hff)
  ["4'h2", "4'hd", "1'h0", "6'h00", "1'h0", "4'h1", "6'h04", "6'h08"] # execute with op code d
  ]

  In order this set of commands does:

• send write with OP_CODE 2 to set the firmware ip2 and clock to 400/10 = 40 MHz
• send OP_CODE 5 = OP_CODE_W_CFG_ARRAY_0 to write to the array. there are 8 bits = 2^8 address. each address has 16 bits of data available. We write to address 0 (8'h0) a 1 (16'h1). We see on the scope a 1 (25ns pulse width) followed by fifteen 0's, which is what we see. Each unit = 25ns because the BXCLK is set to 40 MHz.
• We write to address 1 (8'h1) a 11 (16'h3). We see on the scope two 1's (50ns pulse width) followed by fourteen 0's, which is what we see
• We write to address 2 (8'h7) a 111 (16'h7). We see on the scope three 1's (75ns pulse width) followed by thirteen 0's, which is what we see
• We write to address 3 (8'hf) a 1111 (16'h7). We see on the scope four 1's (100ns pulse width) followed by twelve 0's, which is what we see
• We write to address 5 (8'h5) a 11111111 (16'hff). We first see address 4 skipped = 16 zeros = 400ns. Overall this is twelve 0's = 300ns plus 400ns = 700ns total gap between the previous pulse and this pulse. Then we see this pulse which is eight 1's (200ns width pulse) followed by either 0's, which is what we see.

https://github.com/badeaa3/smartpix-lab-notebooks/assets/13281375/688eaf8c-0c1b-46a4-911b-384c8fcb90f3

Questions:

• we need to understand better the 24 bits of the execute op code

[badeaa3]

We will 2 IP's with 2-3 tests each.

Two tests for shiftRegister are much simpler (IP1).

Three tests for scanChain (IP2):

• test 1: scan chain (look at scanIn). This morning we did Scanchain Figure 8.
• test 2: program 768 registers by injecting charge through entire matrix. look at scanOut after 768 bits.
• test 3: repeat but don't read scanOut and instead read dnn_output

Bits of execute command:

• rest is a mask. 0 = do reset, 1 = don't do
• Loopback test with execute: In execute command enable loop command effectively connects scanIn to scanOut, going through the data registers. This is op code A.
• test number is 1 hot encoded. only scanChain test 1 and test 2 are ready (with 3 not implemented, the fw should not work if you call 3)
• delay shifts when scanIn starts passing down data w.r.t BXCLK falling edge of clock. if we set delay = 0 then scanIn should fire at exactly the rising or falling edge.

3 Tests:

• static_1
• read_cfg_array_0
• write_cfg_array_0 and read_cfg_array_0
• execute with loopback 1 and test r_data_array_0 (2^8 address per) and r_data_array_1
  • 2^8 address * 16 bits per row = 4096
  • scan 768 registers so can do it all on r_data_array_0
  • shift register 5400 registers to program so need 2 arrays

Recording from discussion with Ben https://uchicago.zoom.us/rec/share/-BRLnZ8wU4aYsePpiCMVzaDmtZ3y6XTWmXUMck6N4Dv8Q5n6N_PBg6v_yjjVPxKy.y7-gAARq9q_-rZAI

To test all OP CODES:

• https://github.com/SpacelyProject/spacely-caribou-common-blocks/blob/cg_cms_pix28_fw/cms_pix_28_test_firmware/vrf/fw_ipx_wrap_tb.sv#L90
• https://github.com/SpacelyProject/spacely-caribou-common-blocks/blob/cg_cms_pix28_fw/cms_pix_28_test_firmware/vrf/fw_ipx_wrap_tb.sv#L91
• https://github.com/SpacelyProject/spacely-caribou-common-blocks/blob/cg_cms_pix28_fw/cms_pix_28_test_firmware/vrf/fw_ipx_wrap_tb.sv#L100-L101
• We want to use op code 7 to push array data to sw_read32_0
• op code h'aA R_DATA_ARRAY_0. Write with op code 6, read with op 7, execute with op code D, check sw_read32_1 (status) and verify that it is correct, send op code A

Prepare for v0 chip:

• connect v1 chip level shifter
• verify voltage level coming out of level shifter
• check on shift register firmware

[badeaa3]

Action items.

Software implement tests for the following:

OP_CODE list (GitHub)

typedef enum logic [3:0] {                               // operation_code enumerated type
    OP_CODE_NOOP             = 4'h0,
    OP_CODE_W_RST_FW         = 4'h1,
    OP_CODE_W_CFG_STATIC_0   = 4'h2,
    OP_CODE_R_CFG_STATIC_0   = 4'h3,
    OP_CODE_W_CFG_STATIC_1   = 4'h4,
    OP_CODE_R_CFG_STATIC_1   = 4'h5,
    OP_CODE_W_CFG_ARRAY_0    = 4'h6,
    OP_CODE_R_CFG_ARRAY_0    = 4'h7,
    OP_CODE_W_CFG_ARRAY_1    = 4'h8,
    OP_CODE_R_CFG_ARRAY_1    = 4'h9,
    OP_CODE_R_DATA_ARRAY_0   = 4'hA,
    OP_CODE_R_DATA_ARRAY_1   = 4'hB,
    OP_CODE_W_STATUS_FW_CLEAR= 4'hC,
    OP_CODE_W_EXECUTE        = 4'hD
  } op_code;

• [ ] OP_CODE_NOOP
• [ ] OP_CODE_W_RST_FW
• [x] OP_CODE_W_CFG_STATIC_0 and OP_CODE_R_CFG_STATIC_0
• [x] OP_CODE_W_CFG_STATIC_1 and OP_CODE_R_CFG_STATIC_1
  • op_code_w_cfg_static_1 and op_code_r_cfg_static_1. we tested static_0 with OP codes 2/3, now test static_1 with OP codes 4/5
• [ ] OP_CODE_W_CFG_ARRAY_0 and OP_CODE_R_CFG_ARRAY_0
• [ ] OP_CODE_W_CFG_ARRAY_1 and OP_CODE_R_CFG_ARRAY_1
• [ ] OP_CODE_R_DATA_ARRAY_0 and OP_CODE_R_DATA_ARRAY_1
• [ ] OP_CODE_W_STATUS_FW_CLEAR
• [ ] OP_CODE_W_EXECUTE
  • execute with loopback 1 and test op_code_r_data_array_0 (2^8 address per) and op_code_r_data_array_1

Firmware:

• [ ] shifter register IP1 firmware

Hardware:

• [ ] level shifter for v1 chip
• [x] DUT with v0 chip populated
• [x] DUT with v1 chip populated

[badeaa3]

Improving test for STATIC. Weird thing is I'm seeing the first status register as 4102 instead of the expected 6 now.

> ~r3
<DBG> <2024-06-24 14:40:08> Evaluating: ROUTINE_test_loopback_CFG_STATIC()
Starting register value sw_write32_0 = 570425610
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
Sending OP_CODES: 4'h2, 4'h3
Starting register value sw_write32_0 = 754974719
Write to sw_write32_0: True. Wrote 570425610 and register reads 570425610. hex_list = ["4'h2", "4'h2", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
Write to sw_write32_0: True. Wrote 587202826 and register reads 587202826. hex_list = ["4'h2", "4'h3", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
sw_read32_0 = 266
sw_read32_1 = 4102
Expected in sw_read32_0 ["11'h0", "1'h0", "1'h0", "5'h4", "6'ha"] 266
Starting register value sw_write32_0 = 587202826
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
sw_read32_0 = 0
sw_read32_1 = 0
Sending OP_CODES: 4'h4, 4'h5
Starting register value sw_write32_0 = 754974719
Write to sw_write32_0: True. Wrote 603980042 and register reads 603980042. hex_list = ["4'h2", "4'h4", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
Write to sw_write32_0: True. Wrote 620757258 and register reads 620757258. hex_list = ["4'h2", "4'h5", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
sw_read32_0 = 266
sw_read32_1 = 4120
Expected in sw_read32_0 ["11'h0", "1'h0", "1'h0", "5'h4", "6'ha"] 266
Starting register value sw_write32_0 = 620757258
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
sw_read32_0 = 0
sw_read32_1 = 0
<INF> <2024-06-24 14:40:15> This Routine took: 0:00:07

[badeaa3]

Other good things to do:

• merge request into spacely-asic-config for spacely routines
• merge request into peary for smartpix28