06/27/24

[badeaa3]

Goals:

• [x] 1. work on OP_CODE tests

[badeaa3]

Goal 1

Copying over from #12

OP_CODE list (GitHub)

typedef enum logic [3:0] {                               // operation_code enumerated type
    OP_CODE_NOOP             = 4'h0,
    OP_CODE_W_RST_FW         = 4'h1,
    OP_CODE_W_CFG_STATIC_0   = 4'h2,
    OP_CODE_R_CFG_STATIC_0   = 4'h3,
    OP_CODE_W_CFG_STATIC_1   = 4'h4,
    OP_CODE_R_CFG_STATIC_1   = 4'h5,
    OP_CODE_W_CFG_ARRAY_0    = 4'h6,
    OP_CODE_R_CFG_ARRAY_0    = 4'h7,
    OP_CODE_W_CFG_ARRAY_1    = 4'h8,
    OP_CODE_R_CFG_ARRAY_1    = 4'h9,
    OP_CODE_R_DATA_ARRAY_0   = 4'hA,
    OP_CODE_R_DATA_ARRAY_1   = 4'hB,
    OP_CODE_W_STATUS_FW_CLEAR= 4'hC,
    OP_CODE_W_EXECUTE        = 4'hD
  } op_code;

• [x] OP_CODE_NOOP
• [x] OP_CODE_W_RST_FW
• [x] OP_CODE_W_CFG_STATIC_0 and OP_CODE_R_CFG_STATIC_0
  • Done with ROUTINE_test_loopback_CFG_STATIC
• [x] OP_CODE_W_CFG_STATIC_1 and OP_CODE_R_CFG_STATIC_1
  • Done with ROUTINE_test_loopback_CFG_STATICOP
• [x] OP_CODE_W_CFG_ARRAY_0 and OP_CODE_R_CFG_ARRAY_0
• [x] OP_CODE_W_CFG_ARRAY_1 and OP_CODE_R_CFG_ARRAY_1
• [ ] OP_CODE_R_DATA_ARRAY_0 and OP_CODE_R_DATA_ARRAY_1
• [x] OP_CODE_W_STATUS_FW_CLEAR
• [ ] OP_CODE_W_EXECUTE
  • execute with loopback 1 and test op_code_r_data_array_0 (2^8 address per) and op_code_r_data_array_1

[badeaa3]

Test for OP_CODE_NOOP

• Not actually sure what I'm supposed to see so just returning PASS for now

Executing test routine for OP_CODE_NOOP
*******************************************
Starting register value sw_write32_0 = 754974719
Write to sw_write32_0: True. Wrote 553648127 and register reads 553648127. hex_list = ["4'h2", "4'h0", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
Pass
*******************************************

[badeaa3]

Test for OP_CODE_W_RST_FW

• In sw_read_32_0 expect a 0
• In sw_read32_1 I see https://github.com/Fermilab-Microelectronics/cms_pix_28_test_firmware/blob/main/src/fw_ip2.sv#L179

Executing test routine for OP_CODE_W_RST_FW
*******************************************
Starting register value sw_write32_0 = 553648127
Write to sw_write32_0: True. Wrote 570425343 and register reads 570425343. hex_list = ["4'h2", "4'h1", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
Expected value and actual read from sw_read32_0: 0 and 0 -> Pass
Expected value and actual read from sw_read32_1: 1 and 1 -> Pass
Pass
*******************************************

[badeaa3]

Tests for:

• OP_CODE_W_CFG_STATIC_0 and OP_CODE_R_CFG_STATIC_0
• OP_CODE_W_CFG_STATIC_1 and OP_CODE_R_CFG_STATIC_1

Executing test routine for OP_CODE_W_CFG_STATIC_0, OP_CODE_R_CFG_STATIC_0, OP_CODE_W_CFG_STATIC_1, and OP_CODE_R_CFG_STATIC_1
*****************************************************************************************************************************
Starting register value sw_write32_0 = 570425343
Write to sw_write32_0: True. Wrote 570425343 and register reads 570425343. hex_list = ["4'h2", "4'h1", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]

-------------------------------------------------------------------------------
Executing test routine for OP_CODE_W_CFG_STATIC_0 and OP_CODE_R_CFG_STATIC_0
Starting register value sw_write32_0 = 754974719
Write to sw_write32_0: True. Wrote 570425610 and register reads 570425610. hex_list = ["4'h2", "4'h2", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
Write to sw_write32_0: True. Wrote 587202826 and register reads 587202826. hex_list = ["4'h2", "4'h3", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
Expected value and actual read from sw_read32_0: 266 and 266 -> Pass
Expected value and actual read from sw_read32_1: 6 and 6 -> Pass
Sending OP_CODE_W_STATUS_FW_CLEAR to clean up.
Starting register value sw_write32_0 = 587202826
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
Expected value and actual read from sw_read32_0: 0 and 0 -> Pass
Expected value and actual read from sw_read32_1: 0 and 0 -> Pass
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
Executing test routine for OP_CODE_W_CFG_STATIC_1 and OP_CODE_R_CFG_STATIC_1
Starting register value sw_write32_0 = 754974719
Write to sw_write32_0: True. Wrote 603980042 and register reads 603980042. hex_list = ["4'h2", "4'h4", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
Write to sw_write32_0: True. Wrote 620757258 and register reads 620757258. hex_list = ["4'h2", "4'h5", "11'h0", "1'h0", "1'h0", "5'h4", "6'ha"]
Expected value and actual read from sw_read32_0: 266 and 266 -> Pass
Expected value and actual read from sw_read32_1: 24 and 24 -> Pass
Sending OP_CODE_W_STATUS_FW_CLEAR to clean up.
Starting register value sw_write32_0 = 620757258
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
Expected value and actual read from sw_read32_0: 0 and 0 -> Pass
Expected value and actual read from sw_read32_1: 0 and 0 -> Pass
-------------------------------------------------------------------------------

Pass
*****************************************************************************************************************************

[badeaa3]

Tests for:

• OP_CODE_W_CFG_ARRAY_0 and OP_CODE_R_CFG_ARRAY_0
• OP_CODE_W_CFG_ARRAY_1 and OP_CODE_R_CFG_ARRAY_1

Executing test routine for OP_CODE_W_CFG_ARRAY_0, OP_CODE_R_CFG_ARRAY_0, OP_CODE_W_CFG_ARRAY_1, and OP_CODE_R_CFG_ARRAY_1
*****************************************************************************************************************************
Starting register value sw_write32_0 = 754974719
Write to sw_write32_0: True. Wrote 570425343 and register reads 570425343. hex_list = ["4'h2", "4'h1", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]

-------------------------------------------------------------------------------
Executing test routine for OP_CODE_W_CFG_ARRAY_0 and OP_CODE_R_CFG_ARRAY_0
Starting register value sw_write32_0 = 754974719
Write to sw_write32_0: True. Wrote 637534209 and register reads 637534209. hex_list = ["4'h2", "4'h6", "8'h0", "16'h1"]
Write to sw_write32_0: True. Wrote 654311425 and register reads 654311425. hex_list = ["4'h2", "4'h7", "8'h0", "16'h1"]
Expected value and actual read from sw_read32_0: 1 and 1 -> Pass
Expected value and actual read from sw_read32_1: 96 and 96 -> Pass
Sending OP_CODE_W_STATUS_FW_CLEAR to clean up.
Starting register value sw_write32_0 = 654311425
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
Expected value and actual read from sw_read32_0: 0 and 0 -> Pass
Expected value and actual read from sw_read32_1: 0 and 0 -> Pass
-------------------------------------------------------------------------------

-------------------------------------------------------------------------------
Executing test routine for OP_CODE_W_CFG_ARRAY_1 and OP_CODE_R_CFG_ARRAY_1
Starting register value sw_write32_0 = 754974719
Write to sw_write32_0: True. Wrote 671088641 and register reads 671088641. hex_list = ["4'h2", "4'h8", "8'h0", "16'h1"]
Write to sw_write32_0: True. Wrote 687865857 and register reads 687865857. hex_list = ["4'h2", "4'h9", "8'h0", "16'h1"]
Expected value and actual read from sw_read32_0: 1 and 1 -> Pass
Expected value and actual read from sw_read32_1: 384 and 384 -> Pass
Sending OP_CODE_W_STATUS_FW_CLEAR to clean up.
Starting register value sw_write32_0 = 687865857
Write to sw_write32_0: True. Wrote 754974719 and register reads 754974719. hex_list = ["4'h2", "4'hC", "11'h7ff", "1'h1", "1'h1", "5'h1f", "6'h3f"]
Expected value and actual read from sw_read32_0: 0 and 0 -> Pass
Expected value and actual read from sw_read32_1: 0 and 0 -> Pass
-------------------------------------------------------------------------------

Pass
*****************************************************************************************************************************

[badeaa3]

Tests for OP_CODE_R_DATA_ARRAY_0 and OP_CODE_R_DATA_ARRAY_1

[badeaa3]

Test for OP_CODE_W_STATUS_FW_CLEAR

• This is done within many of the other tests. The functionality is checked explicitly by verifying that sw_write32_0 and sw_read32_0 return to 0 after this op code is sent. If this op code fails, then other test cases would not pass.

[badeaa3]

Test for OP_CODE_W_EXECUTE

[badeaa3]

List of questions for Cristian:

• [ ] OP_CODE_NOOP is there any test to make sure that this works?
• [ ] OP_CODE_W_RST_FW what should I see in sw_read32_0?

[badeaa3]

Current set of instructions to reproduce results.

Step 0

Existing infrastructure at UC:

• a workstation is setup with linux and vivado
• a FPGA is already running petalinux
• you can ssh into the FPGA

• Steps:

• clone the repo following instructions in readme https://github.com/badeaa3/CMSPIX28_DAQ

Flash FPGA

• turn on FPGA without mezzanine connected, verify the LED's on the fpga are set up properly
• once FPGA is on then connect the mezzanine
• go into vivado folder, open vivado, generate bitstream, program FPGA

Compile peary

• scp device onto FGPA, recompile peary with device enabled

Setup spacely

• create virtual environment, edit master config, currently need to edit src/Spacely_Caribou.py for i2c

Test 0 no scope

• run peary, run spacely, run test routine 3

Test 1 with scope

• connect the correct mezzanine pins to the scope, clock divide test, should see clock frequency change

Test 2 with scope

• connect the correct mezzanine pins to the scope, clock divide test, should see delay between bxclk and bxclk_ana change on scope

Test 3 with scope

• set scope to single event mode
• run test to produce pulses on the scope