07/08/24

[badeaa3]

Goals:

• [x] 1. First day back in 1 week. verify that previous tests hold
• [x] 2. Discuss plan with Cristian and Ben for validating IP1 and chip testing -> I want 1-2 results plots to show at ICHEP
• [ ] 3. Understand why pearyd server has an issue when starting from fresh clone of master

[badeaa3]

Goal 1

Executed startup tests.

ROUTINE_startup_test_OP_CODE_NOOP : Pass
ROUTINE_startup_test_OP_CODE_RST_FW : Pass
ROUTINE_startup_test_OP_CODE_CFG_STATIC : Pass
ROUTINE_startup_test_OP_CODE_CFG_ARRAY : Pass
ROUTINE_startup_test_OP_CODE_R_DATA_ARRAY : Pass
Full startup test: Pass
<INF> <2024-07-08 16:17:09> This Routine took: 0:01:37

[badeaa3]

Goal 2

Validating IP1 for ConfigReg:

• IP1 half done. configuration in fast mode to configure all bits with 1 MHz clock.
• there is a new firmware branch.
  • [ ] clone the branch, generate bitstream, flash fpga

Testing ShiftRegister with v1 chip:

• verify that the I/O mapping of the level shifter is correct (I=1.8 V, O=0.9V)
• verify that the I/O between the level shifter and DUT matches the mapping on the DUT
  • [x] ask lou for power cable

Note: to test the v0 chip with this setup will require remapping. I believe that this is very likely worth it to do.

[badeaa3]

When generating bitstream

Update:

• After 1 hour vivado is still in the "Initializing Design" phase of generating the bitstream
• The axi light interface was not pointing to the submodules folder. Cristian will update and push to the dev branch

[badeaa3]

• Finished the day with IP1 flashed to the FPGA.
• If we want to drive pins we will need to go back to IP2 likely.