09/05/2024

[bparpillon]

Goal:

• [x] 1. Reconnect FPGA to chip and spacely: check routines works
• [x] 2. Connect all the analog biases and check current is more or less ~OK
• [x] 3. Program a single pixel and leave everything else to 0
• [x] 4. Setup the pulse generator for charge injection
• [x] 5. Readout pixel scanchain

[bparpillon]

Power went down at Fermilab so I had to cycle through the following setup routine to have the test stand ready:

1. Enable DC supplies (the ASIC supply was turned ON but the output were OFF)
2. remove mezzanine
3. restart FPGA
4. put Mezzanine back
5. Flash FPGA
6. Start Peary server
7. Start Spacely
8. Test

[bparpillon]

Power Bias Current Check: I checked the bias current going in the ASIC. It is supplied through the resistor R4 that is connected between VDDA and PAD_Isource_10uA.
The resistor R4 has a resistance of 44.2Kohm The voltage across R4 is VR4 = 433mV The current bias is 9.72uA which is within 2.8% to the expecting value --> really good

[bparpillon]

The biases have been generated with a breadboard from an existing 5V supply: This setup generates 0.39V for the VMC, VTH is connected directly to 0.92V of VDDD. VTH needs to come from a supply due to it's low impedance input.

[bparpillon]

Pixel programmed: I programmed address 66 of ARRAY_1 to the value 0h0003. This should program a single pixel to the max injection capability.

scan chain: There should NOT be any RESET done from now on! MASK bit for reset in the execute command (bit 23) should be set to 1 Test number bit [15:11] needs to be set to 2 (VERIFY with Cristian)

[bparpillon]

This is the pulse generator we are using:

The Pulse gen is setup in burst mode Vmax = Qinj/Cinj Vmin = 0 Trigger = EXT

https://www.manuallib.com/download//2023-10-16/B&K%20Precision%204063,%204064,%204065%20Function%20Arbitrary%20Waveform%20Generator%20用户手册.pdf

Vin_trigger We need to re-map vin_trigger in the constraint file so that it goes directly to the BNC of the breakout board for a cleaner setup. I hacked the level shifter board to access the trigger before it is level shifted!!!

Green: BxCLK_ANA Red: Vin_test Yellow: BxCLK

[bparpillon]

Status and issues to fix:

1. Scan load is not firing when it is supposed to - check with Cristian if the setup is correct for execute command and for the static array 0 command.
2. The pulse generator when connected to the scope seems to have an attenuation of 1:10 somewhere
3. The pulse generator works only when it connects to the scope, but it doesn't work when it connects with the ASIC

CHECK:

1. It connects to the correct BNC (vin_test)
2. The output is high impedance
3. The scope probe is high impedance
4. The attenuation needs to be checked again

[bparpillon]

I was able to readout the chip using superpixel 1. Superpixel 0 outputs a 1 for every single scan chain bit - I need to check timing settings.

The scan chain and shift register mappings need to be reworked - col[15] for scan chain is col[0] for shift register.