10/10/2024

[bparpillon]

Goals:

• [x] Ben: measure fall edge and arrival time of pulse genin respect to rising edge of BxCLK for different amplitude
• [x] Anthony : connect CarBoard to spacely environment and activate commands
• [ ] Anthony : Create new routine / subroutine to work the carboard pulse generator
• [ ] Ben : Look how to connect this to the FPGA to generate a pulse generator (see ref below)
• [x] Ben, Anthony, Lou: reliably measure rms noise on critical components : VMC, VTH_REF, VDDA.
• [x] Ben: Add a DC generator to separate vdda and vddd
• [ ] Ben: Add LC filter on breadboard to clean the supply
• [ ] Ben: Add RC filter on the breadboard to clean VTH
• [ ] Ben, Anthony, Lou, Cristian: Run the test and leeeetttttt's gooooooooooo

[bparpillon]

Connect CarBoard to spacely:

1. Change the FW constraint file and remap it to the FMC corresponding to INJ_CTLN_1. Need to find the correct mapping value: https://fermicloud.sharepoint.com/:b:/r/sites/FNALO365-ASICDepartment/Shared%20Documents/PROJECTS/CAD/Spacely/Spacely-Caribou/CaR%20Board/CaR_board_v1_5.pdf?csf=1&web=1&e=4y1Zgg Use vin_trigger from FW l INJ_CTRL, and you will need an I2C command to set the bias level of INJ_BIAS.

2. From Adam: Try command sg.INSTR["car"].set_voltage("INJ_1", ) There's a chance this might just work for you, if it doesn't we might need to tweak your Peary install.

3. From Adam: if you need to use more than just INJ_1 (i.e. INJ_2), that will definitely need a Peary tweak. Even if you have the right Peary version, INJ_1 is the only one that's enabled. But it's a very easy tweak.

4. Verify what voltage arrive in the basic, it might not get divided by 2 (careful)

[bparpillon]

Noise Characterization

1. Measure noise without ASIC if bad use it for vddd only
2. Add a power supply to decouple VDDA and VDDD (see pam's message)
3. Add LC filtering to Vdda line
4. Add RC filter to VTH and VMC Line

[bparpillon]

The S-curve issue was resolved:

1. The falling edge of vin_test wasn't completed before BxCLK started sampling the data in the scan chain, thus creating timing violations.
2. We cleaned up the supply noise, isolated analog and dig supplies. Reduced the ground loops. Taped the power cables. Isolated with plastic wrap noisy devices (FPGA, ethernet cables, digital crap)

The S-curve below was the original issue:

The S-curve now looks like this:

[bparpillon]

The S-curve is translated depending on the pixel programming: From left to right: programming 01 (Cinj=1.85fF), 10 (2xCinj), 11 (3xCinj)

This corresponds to respectively (0x2, 0x1 and 0x3) in the shift register because the LSB is sent first which reverse the order.