06/13/24

[badeaa3]

Goals:

• [x] check if S_AXI_ACLK which is connected to pl_clk0 is at ~100MHz which is input to clock divider logic for generating 1MHz ConfigClk
• [ ] Drive the Reset, configIn, and configLoad pins and see them on the scope. This involves software (spacely), c code (peary device), and firmware. Discuss this with Cristian

[badeaa3]

With Ben/Giuseppe realized that the firmware has a logic bug which produces a 500 kHz clock rather than a 1 MHz clock.

The CLK_DIVIDER needs to be set to 50 instead of 100.

Read the following logic to understand the details. https://github.com/SpacelyProject/spacely-caribou-common-blocks/blob/nh_cms28_pix_fw/configReg_interface/src/configReg_interface.sv#L196-L209

 // clock divider logic
  always @(posedge S_AXI_ACLK or negedge S_AXI_ARESETN) begin
    if(~S_AXI_ARESETN) begin
      clk_counter <= 0;
      ConfigClk   <= 0;
    end else begin
      if(clk_counter == CLK_DIVIDER - 1) begin
        ConfigClk <= ~ConfigClk;
        clk_counter <= 0;
      end else begin
        clk_counter <= clk_counter + 1;
      end
    end
  end

[badeaa3]

We are now able to see the 1 MHz clock by setting in the _top.sv file https://github.com/SpacelyProject/spacely-caribou-common-blocks/blob/nh_cms28_pix_fw/configReg_interface/src/configReg_interface_top.v#L20.

parameter integer CLK_DIVIDER = 50,

[badeaa3]

Talked with Cristian:

1. Test Cristian's firmware. Force it into a particular setting where it uses IP2 (scan chain), set clock at 40 MHz, bxclock bxclock_ana delayed by 5ns. If we can see the clocks on the scope then return back to nominal firmware.
2. There are three registers to include in the peary memory map and communicate with software.

[badeaa3]

Saw bxclk and bxclk_ana on the scope. The analog clock is used for the analog portion of the chip, while the bxclk is used for the digital portion. We expected to see them both at 40 MHz with a 5ns delay between them. We actually saw them both at 1 MHz and a 250ns delay between them, a 40x difference in both cases. Investigating this now with Cristian, Ben, Jieun.

[badeaa3]

We see that the clock from pl_clk1 is always at 10 MHz no matter what we set it to.

Two ideas:

• maybe we need to add a constraint in the xdc file -> trying to do create_clock -name PL_CLK1 -period 5.0 [get_ports PL_CLK1] -> didn't work
• can we change the pl_clk0 to a different clock from 100 MHz? If yes then we could reuse it in other places