10/31/24 - DNN and power debug round #3

[bparpillon]

Goals

• [x] extract S-curve on Pixel 0 with max stat and cardboard and see and document the impact
• [ ] probe dnn<0> and dnn<1>
  • [ ]- ideally get a hold on a new scope with 4 working channels. (maybe channel 3 works enough and is just noisy)
• [ ] Compare probed signal with FW response and see which bits seem valid
• [x] Start debugging the power on vddd
  • [ ] Swap with vdda to see if the carboard is off
  • [ ] Ask Chinar for the gate count and a leakage estimate
  • [x] Inspect ESDs
  • [x] Simulate sealring and Padring
• [ ] Make a decision for ASIC PCB
  • [ ] Get the cost breakdown
  • [ ] Get an assembly timing estimate
• [ ] If time allows -> Start looking at other superpixel
• [x] Get the F*** out before 6PM

[bparpillon]

Issues with cardboard biases:

1. S-curve was extracted and exceeds 900e- on pixel 0 bit 0
2. Every pixels' bit 0 fired even if they were not programmed
3. This seems to indicated that the biases line are being pulled down during AZ and can't handle the load even with 10nF of decoupling caps on the ASIC board.

• [ ] Probed the vth voltage and take a screenshot
• [ ] Add filtering and decoupling to mitigate the issue
• [ ] If it is mitigatable - apply change to the new ASIC board

[bparpillon]

New Issue On Carboard biases lines:

The DAC7678 in the cardboard that provides all the biases, is NOT stable with capacitance load greater than 500pF.

We observe a sinusoid in each vth0/1/2 with amplitude 200mV and frequencies around 200KHz because of this instabilities.

To mitigate the problem we added a series resistor of 500Kohm between vth0/1/2 and the ASIC board, but found that the IR drop across the resistor due to input leakage current was too large.

We measured the leakage current to 500nA -the decoupling caps leakage was measured at 3.88pA (testbench tb_dcap_dc), so the leakage source has to be investigated!

We replaced the 500Kohm with 2.2Kohm and confirmed the bias line was very good again. We need to add 2.2Kohm on each bias lines (vth0/1/2 and VMC) and make sure to modify the ASIC board.

[bparpillon]

Ivdd vs vdd:

the plot shows a knee at 0.4V and a slow/linear rise with a slope of roughly 100ohm.

The slope is too slow and the knee to low to look like a DNW diode Schottky knee matches but slope is still too small Maybe big transistor near the DNW form parasitic BJT thyristors?

• [x] Crack up the layout and extract PEX from the top. Look for parasitic diodes and sim with them
• [ ] Look at the dimension of a 100ohm NWELL resistor to assess the size of the structure.
• [ ] Measure current with superpixel 1 and 2 and see if there are any differences.

[bparpillon]

Current from VDDD (blue) and VDDA (red) for superpixel 2:

Current from VDDD (blue) and VDDA (red) for superpixel 1:

[bparpillon]

Extracting PEX - here is a map of where VSSD goes: