11/11/24 - DNN debug #6 - First functional DNN success | PCB board too capacitive | coupling with scanLoad

[bparpillon]

Goals:

• [x] Set the threshold to get reliably zero detection
• [x] Understand why we see the DNN changing consistently right before an injection
• [x] Understand why dnn_output<0> is stuck at 1 - is this a default with no hit
• [x] Extract DNN board capacitance and simulate
• [x] Determine how to interpret the FW dnn_output<1:0> 48-bit readout data
• [x] Try different samples that consistently outputs inference values 1, 2 or 0

[bparpillon]

Random information to remember later when computing the DNN power: Occupancy is 1 hit per mm2 so we think the DNN will get a hit every 6.4MHz. This would help us determine the DNN power.

[bparpillon]

DNN glitches:

We observe DNN glitches befor, during after the injection pulse. See in yellow _dnnout<0> and in green _vintest We think dnn_output<0> is trying to go low during the injection but can't reach 0V because of the capacitive load. However, the glitches before and after the injection are unexplained:

Adding BxCLK plot in red, disconnecting vin_test in green from the ASIC board and using it to trigger the scope, we see that the before and after glitches are still there.

Replacing BXCLK with scanLoad - we see that dnn_output<0> strongly couples with dnn_output:

Couple of possible reasons:

1. scanLoad couples directly to dnn_output in the test setup (ASIC board, cardboard, cables)
2. scanLoad couples to the analog in the ASIC itself

This needs to be investigated

[bparpillon]

Extract DNN board capacitance and simulate

In yellow we see dnn_output<1>, the ASIC output buffers are struggling to drive the load capacitance

The FW extracts eleven '1' for dnn_output<1> without the 10pF load from the scope, and it extracts 9 "1" with the scope. Meaning 10pF load costs us from 2.5ns to 5ns pulse width.

Simulation

Testbench Setup:

The input pulse is provided with the pwl source with a 100ns width The complete Buffer chain is copied from the chip The Load is based of a parametric PCB capacitance followed by a PAD model :

Here is the PAD model detail: L0 = 1nH C0 = 500fF Cpcb is parametric Cprobe=10pF

This give us the following result:

The time constant of the red plot associated with a PCB capacitance of 600pF matches what we see in the test stand.

We conclude the PCB capacitance is in the order of 600pF

[bparpillon]

DNN position when there is no HITs:

I added one inference at the end of test 11 where no HITs are being sent to the DNN and we observe dnn_output<1:0> take the value '01', which exactly matches what we see in the test stands!

[bparpillon]

DNN Patterns findings:

• The ordering of the row in the y-projection is wrong and has to be corrected in software - the screenshot below show the y-projection but the list is upside down.

• Each pattern programmed was tested against the RTL and successfully provided the write answer !!!

• We find there is some resilience in with dead pixels - and that can be observed also in the RTL.

• The two patterns below are symmetrical, but output a different