06/17/24

[badeaa3]

Goals:

• [x] Discuss with Cristian and Ben about the pl logic clock
• [ ] Write to and read from the memory map

[badeaa3]

About the clock.

• we discussed with Jacque and some other guy
• Does petalinux have FPGA manager on it? Need to check on the if the tool exists sudo xmutil on the FPGA -> it does not
• two other programs to try to run xsct and etc
• we need to verify with Adam what is installed on petalinux, did he encounter problems with outputting PL, and discuss how he creates petalinux

[badeaa3]

Trying to figure out the memory map. Adam recommended setting the base address to a different value. In vivado, sources, Address Editor, Network 0, ..., set master base address to 0x04_0000_0000

[badeaa3]

Useful short video from Adam on gen_mem_map() within Spacely to generate a memory map from a txt file. https://github.com/badeaa3/smartpix-lab-notebooks/assets/13281375/17573e25-4d18-459d-8da8-48d77f63a1f5

[badeaa3]

As of end of day we did not successfully create the memory map. Need to work on and understand this better tomorrow.

[badeaa3]

NOTE: we confirmed with Adam on 06/18/24 that in order to set the pl_clk's to different values we need to recreate petalinux and enable this. This is because the PS creates the clocks which petalinux is running on and controlling. He set it himself to pl_clk0 at 100 MHz when creating the petalinux image. He recommends just using the clock wizard. This should be ok and if it is not in the future then we can make a new petalinux image.