06/18/24

[badeaa3]

Goal for the day:

• [x] create working memory map and write to it with spacely

[badeaa3]

Adam, Cristian, and I spoke for a long time about the memory map. I believe we now understand it. Testing it now on the peary device and with spacely.

in a txt file file we put the following:

*BASE 0x0400000000
sw_write32_0,0x0,0xFFFFFFFF,True,True
sw_read32_0,0x4,0xFFFFFFFF,True,False
sw_read32_1,0x8,0xFFFFFFFF,True,False

The BASE address we set via vivado "Address Editor".

The syntax is then: name, offset, mask, read, write.

• name = name visible by spacely software
• offset = offset in the firmware for the memory we would like to access
• mask = mask for the 32 bits (0xFFFFFFFF means unmask all)
• read = boolean if the address is readable
• write = boolean if the address is writeable

Then we generate the memory map using spacely.

source ~/.bashrc
conda activate spacelyvenv
cd /asic/projects/C/CMS_PIX_28/testing/spacely/PySpacely
python Spacely.py
# click enter
gen_mem_map()

select the txt file from the browser that opens. Then spacely returns the memory map:

> gen_mem_map()
<DBG> <2024-06-18 17:38:32> Executing "gen_mem_map()" as code
#define FPGA_REGS \
 { \
  {"sw_write32_0", {FPGA_MEM, register_t<size_t>(0x000000, 0xffffffff, true, true, false)}}, \
  {"sw_read32_0", {FPGA_MEM, register_t<size_t>(0x000000, 0xffffffff, true, true, false)}}, \
  {"sw_read32_1", {FPGA_MEM, register_t<size_t>(0x000020, 0xffffffff, true, true, false)}}, \
}

We then copy-pasted those lines into the peary device memory map section here, scp'd the device to the ZCU petalinux, and recompiled peary.

[badeaa3]

Success!! We have successfully read from and written to a register in firmware via software: spacely (python) <-> peary <-> axi interface <-> firmware

[badeaa3]

https://github.com/badeaa3/smartpix-lab-notebooks/assets/13281375/4e7d8679-8297-453b-a9c7-64811667be9d

[badeaa3]

Next step is to try to write to this register sw_write32_0 an actual configuration code (32 bit word). This should put the firmware in a state to generate the blck and blck_ana at 40 mhz offset by 5ns. The code is 4'h2, 4'h2, 11'h0, 1'h0, 1'h0, 5'h4, 6'hA

The first two entries 4'h2 4'h2 are the firmware ID.

[badeaa3]

With help of Giuseppe. Converting the code to int.

{4'h2, 4'h2, 11'h0, 1'h0, 1'h0, 5'h4, 6'hA}
00100010000000000000000100001010
570425610

Then I wrote it with spacely and this should trigger the firmware to produce the 40 MHz blck and blck_ana. And it did! The waveforms are not pretty yet (they can be cleaned up) ... but you see the two 40 MHz clocks that are separated by 10ns offset (because of what we set in the firmware).

[badeaa3]

We are now going to try to set different periods, delay, sign for the clocks within the firmware.

[badeaa3]

• [x] write python script
• [x] leave this 4'h2, 4'h2, 11'h0, 1'h0, 1'h0, 5'h4, 6'hA but vary the last 6'hA from 10 to 40. We should see on the clock it go from 400/10=40 MHz to 400/40=10 MHz. wait 5 seconds between looping (it would be great to save the scope)
• [x] then change the 2nd parameter 5'h4 (4 = 4 ticks of 400 MHz. 4*2.5ns = 10ns). We can vary this up to half of the clock period set by the last configuration (6'hA). This is why the delay has 5 bits, because the delay also has a sign. For example, if 6'hA makes a 40 MHz clock and we can generate an offset up to half to the period.
• [x] the third parameter (right to left) 1'h0 controls the sign. if we write 1'h1 which will make the offset negative (rising edge of analog clock and the falling edge of the digital clock)

[badeaa3]

There are a set of tests written by Cristian here /asic/projects/C/CMS_PIX_28/abadea/spacely-caribou-common-blocks/cms_pix_28_test_firmware/vrf/fw_ipx_wrap_tb.sv

[badeaa3]

Wrote a short script to convert the hex list into an int that we can write with spacely. Used this to change the 40 MHz clock to a 10 MHz one by setting the clk_divide from 6'hA =10 to 6'h28 =40. Changes pushed to GitHub in the spacely routine https://github.com/Fermilab-Microelectronics/spacely-asic-config/blob/badea_041224/SMARTPIX28/SMARTPIX28_Routines.py#L102-L119

clk_divide = "6'h28" # divide the overall 400 MHz clock by 40 instead of 10 from "6'hA"
hex_list = ["4'h2", "4'h2", "11'h0", "1'h0", "1'h0", "5'h4", clk_divide]
temp = gen_sw_write32_0(hex_list) # custom program by us
sw_write32_0 = sg.INSTR["car"].set_memory("sw_write32_0", temp)

[badeaa3]

To-do's next:

• The set of test recommended by Cristian above
• Clean up the branches on the firmware repo. I pushed anything that I edited in the firmware (starting from ben’s branch, which came from cristians branch) into my own branch ab_cms_pix28_fw https://github.com/SpacelyProject/spacely-caribou-common-blocks/tree/ab_cms_pix28_fw/cms_pix_28_test_firmware. Major to-do is to clean up how we do this also
• Make a testing plan with Giuseppe/Ben/Cristian
• Reproduce the tests/results from the v0 chip