06/19/24

[badeaa3]

Goals:

• [x] work through Cristian's tests
• [ ] see if it is possible to record the scope on the computer -> We need a USB to USB connector in order to do this. Ask Pam/Paul for this tomorrow.
• [ ] prepare generally for scan chain v0 to be done tomorrow. the exact test plan and other infrastructure needed for it

[badeaa3]

Reading about getting the scope to the computer.

• This is our scope https://www.keysight.com/us/en/product/MSO7054A/mixed-signal-oscilloscope-500-mhz-4-analog-plus-16-digital-channels.html
• This looks like a set of instructions https://user.eng.umd.edu/~tretter/commlab/c6713slides/ScopeCapture.pdf

I will continue with the other tests then come back to this as the testing structure solidifies.

-> We need a USB to USB connector in order to do this. Ask Pam/Paul for this tomorrow.

[badeaa3]

Test 1 :

• leave this 4'h2, 4'h2, 11'h0, 1'h0, 1'h0, 5'h4, 6'hA but vary the last 6'hA from 10 to 40. We should see on the clock it go from 400/10=40 MHz to 400/40=10 MHz. wait 5 seconds between looping (it would be great to save the scope)

Results:

• Below you can see the screenshot of the linux machine desktop where spacely executes the routine ROUTINE_clk_divide() to write to sw_write32_0 and a recording of the scope when this happens.
• The scope is looking at the BxCLK_ana (green) and BxCLK (yellow) pins on the mezzanine connected to the FMC port of the FPGA.

https://github.com/badeaa3/smartpix-lab-notebooks/assets/13281375/64d1ba58-c751-46aa-ae99-286d2a025872

NOTE: Something weird happens at second 30 into the video and this consistently happens.

[badeaa3]

Test 2:

• then change the 2nd parameter 5'h4 (4 = 4 ticks of 400 MHz. 4*2.5ns = 10ns). We can vary this up to half of the clock period set by the last configuration (6'hA). This is why the delay has 5 bits, because the delay also has a sign. For example, if 6'hA makes a 40 MHz clock and we can generate an offset up to half to the period.
• the third parameter (right to left) 1'h0 controls the sign. if we write 1'h1 which will make the offset negative (rising edge of analog clock and the falling edge of the digital clock)

Results:

• Below you can see the screenshot of the linux machine desktop where spacely executes routine ROUTINE_clk_delay() to write to sw_write32_0 and a recording of the scope when this happens.
• The scope is looking at the BxCLK_ana (green) and BxCLK (yellow) pins on the mezzanine connected to the FMC port of the FPGA.

https://github.com/badeaa3/smartpix-lab-notebooks/assets/13281375/ae54d531-ca85-4250-9a71-036ccf1346ab

[badeaa3]

This completes the 3 tests that Cristian and I discussed on 06/18/24 as listed at the bottom of #6

Spacely code:

• clk divide routine https://github.com/Fermilab-Microelectronics/spacely-asic-config/blob/badea_041224/SMARTPIX28/SMARTPIX28_Routines.py#L68
• clk delay routine https://github.com/Fermilab-Microelectronics/spacely-asic-config/blob/badea_041224/SMARTPIX28/SMARTPIX28_Routines.py#L93

[badeaa3]

Request from Giuseppe: can we have a square waveform for the clock?

• I think we need to cleanup the waveform to make this happen. Will try to debug with Ben
• Ben says: "Wondering if the fpga has issue loading the 20pF scope probe, maybe we can try an active probe tmr."