06/20/24

[badeaa3]

Goals:

• [ ] get USB to USB cable to connect scope to computer so that we can:
  • screen record with the peary, spacely, and oscilloscope running at the same time
  • so that we can see the scope while ssh'd into the computer
• can we have a square waveform for the clock? likely need to cleanup the signal to the scope - try changing xdc constraint file to increase drive capability to 16mA. -> we fixed a bit the shape by putting shorter ground loops. Will see what it looks like after the level shifter.
• [ ] peary is still somehow magic to us. We need to understand better how peary allows the PS to talk to the PL
• [ ] verify the voltage coming out of the FPGA is 2.4 V (or 3V?) and the level shifter is 0.9 V. The chip expects 0.9 V in
• [ ] test v0 chip Scanchain
• [ ] Decide what to discuss on friday meeting

[badeaa3]

From Ben a summary of the steps to test the Scanchain:

This corresponds to Figure 8 from the test manual:

1. BxCLK = 10MHz - 40MHz
2. Reset_not to pulse low to reset the registers in the chip (not the registers in the FW)
3. scanIn to pulse high for at least a BxCLK cycle. scanIn should go high at the falling edge of BxCLK, and go low again at the next rising edge.
4. Count 676 BxCLK cycle and scanOut will pulse high for a single clock cycle. scanOut comes from v0 or v1 chip.

Comments:

• This demonstrates that we can successfully propagated scanIn data through the entire 676 Scanchain registers
• This demonstrates that we can use the Scanchain to output the pixel data.
• Next step is to sample the pixel data in the Scanchain and push it out in the scanOut. This is more complicated

[badeaa3]

Section 9 describes how to connect the scope to a computer https://www.rftesolutions.com/pdf/oscilloscopes/DSO6012A--Users_Guide.pdf

[badeaa3]

FW notes:

• IP1 = configReg (neha)
• IP2 = scanChain (Cristian)
• IP3 = DNN (Cristian)

[badeaa3]

hex code = 4'h2, 4'h2, 11'h0, 1'h0, 1'h0, 5'h4, 6'hA

First byte

• 1st number = firmware ID
• 2nd = operation code

Other 3 bytes:

• 3rd = data number (if op code is static) OR data address (if op code is an array)

verify that we can read the register from sw_read32_0 and sw_read32_1. The 3 bytes stored in here should match the least significant (LSB) 3 bytes from sw_write32_0

Every clock cycle create 768 bits and read it out every clock cycle

[badeaa3]

• send OP code 2 through sw_write32_0
• send OP code 3 through sw_write32_0
• read from sw_read32_0 N number of times
• op code 6 for writing the array
• send OP code 3 to read Then
• send OP code execute

[badeaa3]

• write a pattern with OP code 2, then send op code EXECUTE the details are inside of fw_ipx_wrap_tb

[badeaa3]

execute OP code, the last three bytes = test delay, sample, number, loopback

[badeaa3]

Test 1

• Write with op code 6 data packets to increase the pulse width on the scope
• spacely ROUTINE_scanChain_counter

Expectation: we should see pulses of various shapes from the scan_in pin 23 on the scope Result: we do not see any pulses

[badeaa3]

Test 2

• hard coded into the firmware assign reg_rddin[1] = 32'h12345678 and we tried to read back sw_read32_0 from the memory map

Result: we still read back 0 Thoughts: this sounds like the memory map is wrong