06/21/24

[badeaa3]

• [ ] read from sw_read32_0 and sw_read32_1 -> discussed with Adam see comment below
• [ ] see the scanChain counter working on the scope -> discussed with Cristian see comment below
• [x] get scope connected to the computer
  • screen record with the peary, spacely, and oscilloscope running at the same time so that we can see the scope while ssh'd into the computer
• [x] unify firmware GitHub branches -> working with Cristian to do this

[badeaa3]

Pam helped setup the correct IP and gate for the clock to be seen on the computer.

• LAN Address menu
• set value to be consistent with FPGA
• set the final value
• set the gateway to 11

Now you can see it. Open Firefox and search for the scope IP address below

But I cannot open the Remote Front Panel from the Browser Web Controller because Java is disabled.

IP ADDRESS FOR SCOPE: 192.168.1.20

[badeaa3]

Cristian is having trouble generating the bitstream even though it works on the linux machine with FPGA connected to it.

[badeaa3]

We discussed the spacely and peary side for the sw_read32_0 with Adam. He believes that what we have looks good and that it is possibly the firmware.

[badeaa3]

I saw a weird bug.

1. I git clone the firmware repo and go to ab_cms_pix28_fw branch (last push on June 18th). generate bitstream and export hardware. flash fpga. routine 1 clk_divide works properly
2. I change assign reg_rddin[1] = sw_read32_0 to assign reg_rddin[1] = 32'h12345678. generate bitstream and export hardware. flash fpga. routine 1 clk_divide stops working properly. every other sw_write to change the clock frequency does not produce the right frequency on the scope.
3. I revert the change. generate bitstream and export hardware. flash fpga. routine 1 clk_divide works again

[badeaa3]

Get list of resources used on linux machine ps aux | awk '{print $6/1024 " MB\t\t" $11}' | sort -n

[badeaa3]

For the scanChain counter. It turns out that Cristian updated the OPCODEs so the hex_lists that we were writing into sw_write32_0 are outdated. We need to fix this once we align on one firmware.

[badeaa3]

Cristian got a working branch cg_cms_pix28_fw. We need to submit a merge request to get this branch into master, delete ab and bp branches, then start new.

Cloned repo and check out the branch in /asic/projects/C/CMS_PIX_28/abadea/temp/spacely-caribou-common-blocks. Generated the bitstream and ran the two standard tests:

• routine 1 clk_divide: PASS (video 1)
• routine 2 clk_delay: PASS (video 2)

The branch is ready to be merged into master.

This picture is of the spacely terminal where you can see that sw_write32_0 can be written to AND read from.

https://github.com/badeaa3/smartpix-lab-notebooks/assets/13281375/34a1a563-25a6-4cba-9c24-3e02abbaabce

https://github.com/badeaa3/smartpix-lab-notebooks/assets/13281375/5351a1fd-0772-4eca-bc94-509c0e6a0049