Moving average wrong behaviour

smartbench / hdl

Smartbench project - FPGA HDL (Verilog)

1 stars 0 forks source link

Open akukulanski opened 6 years ago

akukulanski commented 6 years ago

Doesn't work correctly with maximum decimation. (Because of wrong sizes in wires/regs)

akukulanski commented 6 years ago

working on it on branch 'rev1_correcting_moving_average'