Currently the Makefile is hardcoded to use gcc, which doesn't work nicely if the user isn't using gcc to compile their software (eg if they're using clang, or if they need to invoke a different gcc for cross-compilation).
Makefiles support the $(CC) variable (standard behaviour, not a new feature or anything), which defaults to cc (which is an alias to gcc on most systems). The advantage to using this is that it can be overridden with environment variables, allowing the user to select the compiler without having to edit the Makefile.
Currently the Makefile is hardcoded to use
gcc
, which doesn't work nicely if the user isn't using gcc to compile their software (eg if they're usingclang
, or if they need to invoke a differentgcc
for cross-compilation).Makefiles support the
$(CC)
variable (standard behaviour, not a new feature or anything), which defaults tocc
(which is an alias togcc
on most systems). The advantage to using this is that it can be overridden with environment variables, allowing the user to select the compiler without having to edit the Makefile.