VHDL is case insensitive, but regexps are not

sneakypete81 / atom-vhdl-entity-converter

Convert a VHDL entity into a component, instance or signal definitions, using the clipboard.

https://atom.io/packages/vhdl-entity-converter

GNU General Public License v3.0

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Closed svenn71 closed 8 years ago

svenn71 commented 8 years ago

Just a note that you should make all text matching in regexps case insensitive. Just replace port with Port and ports are not detected.

sneakypete81 commented 8 years ago

Good point, thanks.