Open Wits15730 opened 6 months ago
Every register has only binary value. No concept of sign exists in register. However, in specific instruction, value in register is regarded as signed or unsigned with that binary representation.
So in assert_eq instruction, though r3 looks like unsigned large value, it actually is binary representation of -2. In comparison with option slt, value in r3 will be regarded as -2.
Yes.. I forgot to mention that I tried assert_eq r1 0
and it failed. That is, r3 was not regarded as -2, but actual value 4294967294. This led to the branching to a block where vector loading happened(from inaccessible memory), and I got the error
Your assembly fails with following Error
While running matmul_vectorized, following error occurs
-------------------------------------------------
Error occurs while trying to access adress 204824 : line 185
-------------------------------------------------
: line 147
The above issue is a discussion of the reason I found was causing the error.
-Minimum Reproducing Example run the below program(which was generated by the swpp compiler) with the interpreter, with input from matmul1/test/input1.txt
start matmul 4:
.entry:
r2 = const 0
r3 = const 1
r5 = mul r2 r3 32
r4 = const 8
br .for.cond
.for.cond:
r1 = icmp ult r5 arg1 32
br r1 .for.body .for.end22
.for.body:
r6 = mul r2 r3 32
br .for.cond1
.for.cond1:
r1 = icmp ult r6 arg1 32
br r1 .for.body3 .for.end19
.for.body3:
r8 = mul r2 r3 32
r7 = mul r2 r3 64
br .for.cond4
.for.cond4:
r1 = icmp ult r8 arg1 32
br r1 .for.body6 .for.end
.for.body6:
r1 = mul r5 arg1 32
r1 = add r1 r8 32
r1 = mul r1 r4 64
r1 = add arg3 r1 64
r9 = load 8 r1
r1 = mul r8 arg1 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg4 r1 64
r1 = load 8 r1
r1 = mul r9 r1 64
r7 = add r7 r1 64
br .for.inc
.for.inc:
r8 = add r8 r3 32
br .for.cond4
.for.end:
r1 = mul r5 arg1 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg2 r1 64
store 8 r7 r1
br .for.inc17
.for.inc17:
r6 = add r6 r3 32
br .for.cond1
.for.end19:
br .for.inc20
.for.inc20:
r5 = add r5 r3 32
br .for.cond
.for.end22:
ret
end matmul
start read_mat 2:
.entry:
r2 = const 0
r3 = const 1
r5 = mul r2 r3 32
r4 = const 8
br .for.cond
.for.cond:
r1 = icmp ult r5 arg1 32
br r1 .for.body .for.end6
.for.body:
r6 = mul r2 r3 32
br .for.cond1
.for.cond1:
r1 = icmp ult r6 arg1 32
br r1 .for.body3 .for.end
.for.body3:
r7 = call read
r1 = mul r5 arg1 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg2 r1 64
store 8 r7 r1
br .for.inc
.for.inc:
r6 = add r6 r3 32
br .for.cond1
.for.end:
br .for.inc4
.for.inc4:
r5 = add r5 r3 32
br .for.cond
.for.end6:
ret
end read_mat
start print_mat 2:
.entry:
r2 = const 0
r3 = const 1
r5 = mul r2 r3 32
r4 = const 8
br .for.cond
.for.cond:
r1 = icmp ult r5 arg1 32
br r1 .for.body .for.end6
.for.body:
r6 = mul r2 r3 32
br .for.cond1
.for.cond1:
r1 = icmp ult r6 arg1 32
br r1 .for.body3 .for.end
.for.body3:
r1 = mul r5 arg1 32
r1 = add r1 r6 32
r1 = mul r1 r4 64
r1 = add arg2 r1 64
r1 = load 8 r1
call write r1
br .for.inc
.for.inc:
r6 = add r6 r3 32
br .for.cond1
.for.end:
br .for.inc4
.for.inc4:
r5 = add r5 r3 32
br .for.cond
.for.end6:
ret
end print_mat
start main 0:
.entry:
r2 = call read
r1 = mul r2 r2 32
r3 = const 8
r1 = mul r1 r3 64
r4 = malloc r1
r1 = mul r2 r2 32
r1 = mul r1 r3 64
r5 = malloc r1
r1 = mul r2 r2 32
r1 = mul r1 r3 64
r1 = malloc r1
call read_mat r2 r4
call read_mat r2 r5
call matmul_vectorized r2 r1 r4 r5
call print_mat r2 r1
r1 = const 0
ret r1
end main
start matmul_vectorized 4:
.entry:
r2 = const 3
r3 = sub arg1 r2 32
r4 = const 0
r5 = const 1
r9 = mul r4 r5 32
r6 = const 8
r7 = const 4
r8 = const 2
br .for.cond
.for.cond:
r1 = icmp ult r9 arg1 32
r10 = mul r4 r5 32
br r1 .for.cond1 .for.end22
.for.cond1:
r1 = icmp ult r10 arg1 32
br r1 .for.body3 .for.end19
.for.body3:
v1 = vbcast r4 64
r13 = mul r4 r5 32
br .for.cond4
.for.cond4:
r1 = icmp slt r13 r3 32
r11 = mul r4 r5 64
r12 = mul r13 r5 32
br r1 .for.body6 .for.remain
.for.body6:
r1 = mul r9 arg1 32
r1 = add r1 r13 32
r1 = mul r1 r6 64
r1 = add arg3 r1 64
v2 = vload r1
r1 = mul r13 arg1 32
r1 = add r1 r10 32
r1 = mul r1 r6 64
r1 = add arg4 r1 64
v3 = vload r1
v2 = vmul v2 v3 64
v1 = vadd v1 v2 64
br .for.inc
.for.inc:
r13 = add r13 r7 32
br .for.cond4
.for.remain:
r1 = icmp ult r12 arg1 32
br r1 .for.remain.add .for.remain.end
.for.remain.add:
r1 = mul r9 arg1 32
r1 = add r1 r12 32
r1 = mul r1 r6 64
r1 = add arg3 r1 64
r13 = load 8 r1
r1 = mul r12 arg1 32
r1 = add r1 r10 32
r1 = mul r1 r6 64
r1 = add arg4 r1 64
r1 = load 8 r1
r1 = mul r13 r1 64
r11 = add r1 r11 64
br .for.remain.loop
.for.remain.loop:
r12 = add r12 r5 32
br .for.remain
.for.remain.end:
br .for.end
.for.end:
r1 = mul r9 arg1 32
r1 = add r1 r10 32
r1 = mul r1 r6 64
r1 = add arg2 r1 64
r12 = vextct v1 r4 64
r13 = vextct v1 r5 64
r14 = vextct v1 r8 64
r15 = vextct v1 r2 64
r12 = add r12 r13 64
r13 = add r14 r15 64
r12 = add r12 r13 64
r11 = add r12 r11 64
store 8 r11 r1
br .for.inc17
.for.inc17:
r10 = add r10 r5 32
br .for.cond1
.for.end19:
br .for.inc20
.for.inc20:
r9 = add r9 r5 32
br .for.cond
.for.end22:
ret
end matmul_vectorized
I see. There's an error while running icmp instrunction. It will be fixed soon.
Fixed in latest patch
In my asm file, I have the commands
assert_eq arg1 1
r2 = const 3
r3 = sub arg1 r2 32
assert_eq r13 0
assert_eq r3 r4
--- line 180The problem is that r1 should not be 1, yet it is.
r1 = icmp slt r13 r3 32
with the following assertion error: Assertion Failed. Right side has value 0 while left side has value 4294967294 : line 180
r3 should be -2, since it is 1 - 3. But it is 4294967294. Maybe the i32 value is not sign extended when it is a negative number, and put in the register as an 'unsigned' i32 value.
The .ll code that generated this assembly file (r1 = icmp slt r13 r3 32) reads
%cmp5 = icmp slt i32 %k.0, %dim_minus_3