`make build` to run synthesis is failed.

[zflcs]

When I used the makefile in fpga subdir, I got an error.

➜  fpga git:(main) make build 
rm -rf /home/zfl/workspace/AnTiQ/fpga/build /home/zfl/workspace/AnTiQ/fpga/reports/240116_194056_util_reports
mkdir -p /home/zfl/workspace/AnTiQ/fpga/build /home/zfl/workspace/AnTiQ/fpga/reports/240116_194056_util_reports
cd /home/zfl/workspace/AnTiQ/fpga/build && \
vivado -mode batch "-notrace" -source /home/zfl/workspace/AnTiQ/fpga/tcl/synth.tcl

****** Vivado v2022.2 (64-bit)
  **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
  **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source /home/zfl/workspace/AnTiQ/fpga/tcl/synth.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/zfl/software/xilinx/Vivado/2022.2/data/ip'.
create_ip: Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2385.605 ; gain = 1051.203 ; free physical = 23045 ; free virtual = 28856
INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_0'...
INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'clk_wiz_0'...
INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'clk_wiz_0'...
INFO: [IP_Flow 19-1686] Generating 'Implementation' target for IP 'clk_wiz_0'...
INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'clk_wiz_0'...

=====================================================================================
Running Synthesis for DATE_WIDTH=8 and QUEUE_DEPTH is 32
SYNTH_RUN name: syn_dwidth_8_qdepth_32
=====================================================================================

INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run syn_dwidth_8_qdepth_32. Auto-incremental flow will not be run, the standard flow will be run instead.
[Tue Jan 16 19:41:11 2024] Launched clk_wiz_0_synth_1...
Run output will be captured here: /home/zfl/workspace/AnTiQ/fpga/build/hw_pq_fpga/hw_pq_fpga.runs/clk_wiz_0_synth_1/runme.log
[Tue Jan 16 19:41:11 2024] Launched syn_dwidth_8_qdepth_32...
Run output will be captured here: /home/zfl/workspace/AnTiQ/fpga/build/hw_pq_fpga/hw_pq_fpga.runs/syn_dwidth_8_qdepth_32/runme.log
[Tue Jan 16 19:41:11 2024] Waiting for syn_dwidth_8_qdepth_32 to finish...

*** Running vivado
    with args -log pq_fpga_top.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source pq_fpga_top.tcl

****** Vivado v2022.2 (64-bit)
  **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
  **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source pq_fpga_top.tcl -notrace
Command: synth_design -top pq_fpga_top -part xcvu9p-flga2104-2L-e -flatten_hierarchy none
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xcvu9p'
INFO: [Device 21-403] Loading part xcvu9p-flga2104-2L-e
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 22410
INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [/home/zfl/software/xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
ERROR: [Synth 8-36] 'TIME_WIDTH' is not declared [/home/zfl/workspace/AnTiQ/src/array_pq/pq.sv:11]
INFO: [Synth 8-10285] module 'pq' is ignored due to previous errors [/home/zfl/workspace/AnTiQ/src/array_pq/pq.sv:113]
INFO: [Synth 8-9084] Verilog file '/home/zfl/workspace/AnTiQ/src/array_pq/pq.sv' ignored due to errors
Failed to read verilog '/home/zfl/workspace/AnTiQ/src/array_pq/pq.sv'
INFO: [Common 17-83] Releasing license: Synthesis
9 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Tue Jan 16 19:41:56 2024...
[Tue Jan 16 19:42:00 2024] syn_dwidth_8_qdepth_32 finished
WARNING: [Vivado 12-13638] Failed runs(s) : 'syn_dwidth_8_qdepth_32'
wait_on_runs: Time (s): cpu = 00:00:43 ; elapsed = 00:00:48 . Memory (MB): peak = 2393.711 ; gain = 0.000 ; free physical = 23078 ; free virtual = 28881
Run is defaulting to parent run srcset: sources_1
Run is defaulting to parent run constrset: constrs_1
Run is defaulting to parent run part: xcvu9p-flga2104-2L-e
ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_dwidth_8_qdepth_32' due to failures in the following run(s):
syn_dwidth_8_qdepth_32
These failed run(s) need to be reset prior to launching 'impl_dwidth_8_qdepth_32' again.

INFO: [Common 17-206] Exiting Vivado at Tue Jan 16 19:42:00 2024...
make: *** [Makefile:15：build] 错误 1

[zflcs]

The TIME_WIDTH and TW arguments are not correct. Besides, the push_id_o in fpga/rtl/pq_fpga_top.sv should be push_id_i and its direction is input.

[ANurmi]

Hi @zflcs, sorry for the slow response! Indeed, the FPGA files were out of date with naming, everything should be fixed now on main (commit a260ec875f13b0a1526d1d180fce5c6b1448c0c0).