SDRAM Memory Address on HPC VP

[andstepan]

In documentation it is stated that "External Addresses" are mapped at address 0x1_0000_0000. In the VP's hpc.repl file, they are mapped at 0x1000_0000. Can we see what's going on?

[hegza]

Meeting outcomes

Memory map investigation

• HPC needs the 0x1_0000_0000 "External access", when acting as the initiator, to access locations outside of the HPC subsystem
• HPC as initiator:
  • SDRAM starts at 0x1_0000_0000
  • This has the external bit at 0x1_0000_0000 + SDRAM base at 0x0
  • SDRAM len is 0x7000_0000
  • HPC internal configurations are available via local map in locations 0x0..0x1_0000_0000 and via global map at 0x1_0000_0000 + HPC_config offset.
• SysCtrl as initiator:
  • SDRAM starts at 0x1000_0000
  • The first 0..0x1000_0000 are unavailable on SysCtrl due to legacy memory map.
  • HPC configurations are available via global map at HPC_config
  • SDRAM len (truncated) is 0x6000_0000

Implementation on Renode (hardware view)

• common.repl

  sdram_truncated: Memory @ {
  sysbus new Bus.BusPointRegistration { address: 0x1000_0000; cpu: cpu_sysctrl };
  sysbus new Bus.BusPointRegistration { address: 0x1_1000_0000; cpu: cpu_hpc0, cpu_hpc1, cpu_hpc2, cpu_hpc3 };
  }
  size: 0x6000_0000

• hpc.repl

  // HPC-only visible part of the SDRAM
  sdram_hpc: Memory @ {
  sysbus new Bus.BusPointRegistration { address: 0x1_0000_0000; cpu: cpu_hpc0, cpu_hpc1, cpu_hpc2, cpu_hpc3 };
  }
  size: 0x1000_0000

Impl in link script (software view)

// hpc-sdram.ld
MEMORY {
  SDRAM : ORIGIN = 0x1_0000_0000, LENGTH = 0x7000_0000 
}

// sysctrl-sdram.ld
MEMORY {
  SDRAM : ORIGIN = 0x1000_0000, LENGTH = 0x6000_0000 
}

[hegza]

We confirmed in the meeting today that the above is correct.

[hegza]

Correction: SysCtrl does not need the 0x1_0000_0000 external access bit to read from HPC configurations. (fixed in original message)

[hegza]

Closing non-actionable issue in favor of a wiki page: https://github.com/soc-hub-fi/headsail-vp/wiki/Headsail-memory-maps