Closed vilukissa68 closed 3 months ago
I reverted all changes related to DLA. The VP memory should now have almost 1-to-1 correspondence to ASIC except PLIC being larger. Larger DLA examples fail due to them not fitting into the bootram, this issue will be fixed in the future when a suitable solution is found.
Adds external bit addressing for HPC in VP and BSP. This solution modifies read and write methods in BSP so that all HPC operation addresses are preceded with
0x1_0000_0000
to ensure similar functionality as described in issue https://github.com/soc-hub-fi/headsail-vp/issues/33. New addresses in drivers should be defined from the Sysctrl point of view, which then gets automatically addressed with the external bit on HPC. These changes required the DLA driver to utilize BSP read/write operation, which was not the case before.Previously VP was described in
common.repl
,hpc.repl
andsysctrl.repl
, due to new dependencies imposed by the shadowed sdram these files have been concatenated into oneheadsail.repl
file, which now encompasses the whole VP. HPC memory regions are now preceded by0x1_0000_0000
.