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soc-hub-fi / headsail-vp

Headsail — Virtual Platform
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Possibly incorrect SRAM locations & lengths #76

Open hegza opened 1 month ago

hegza commented 1 month ago

Relevance

Relevant for OpenSBI. We disabled these memories in OpenSBI (Andreas' WIP port) for now.

Problem statement

REPL describes 4 RAMs named ram_{0..=3}: https://github.com/soc-hub-fi/headsail-vp/blob/6eb01d55fc39222507f4a02e2a1ec2b352516867/vp/devel/headsail.repl#L124-L158

Are these same as Shared Sram memory bank 0..=3 in global memory map: https://soc-hub.gitlab-pages.tuni.fi/headsail/hw/headsail/address_map.html?

The addresses seem wrong. git blame points that @vilukissa68 might know what's going on. Could you look into it?

hegza commented 1 month ago

Highlighting @andstepan for visibility.

hegza commented 1 month ago

Checking the RTL code, the documented SRAM addresses seem correct: https://gitlab.tuni.fi/soc-hub/headsail/hw/interconnect-ss/-/blob/main/rtl/interconnect_core.v#L1597

vilukissa68 commented 1 month ago

I have no idea why, but banks 1..=3 are clearly mapped to the wrong addresses. I opened PR #77 to fix this issue.

hegza commented 1 month ago

@vilukissa68 I found the problem: https://github.com/soc-hub-fi/headsail-vp/blob/main/vp/kactus2-generated-2023-10-12-ibex/Ibex_memory.repl

It's from Kactus2. It's an IP-XACT modeling error that propagated to our model. I'll open an issue with Headsail hardware repository.

hegza commented 1 month ago

Tracking issue at Headsail HW: https://gitlab.tuni.fi/soc-hub/headsail/hw/headsail/-/issues/34

Will close, after all instances mentioned in above issue are fixed.