Closed in3otd closed 5 years ago
FYI, Johan wrote me that he also was not seeing the PWM output but was able to fix it using the a locally generated clock at 122.88 MHz for the TX interpolating filter instead of the clk
at 76.8 MHz.
I think the issue is due to the EER_req
enable signal for the FIR, which is just two clock cycles wide at 245.76 MHz which will be sampled with clk
at 76.8 MHz, so it may be missed, depending on how the two clocks are aligned.
So a solution could be either to increase the EER_req
to 4 cycles or to increase the FIR clock as done by Johan. In this latter case we could probably use clk_2x
and maybe even reorganize the filter to use less resources at double speed, as done for the RX FIR recently.
I've added the Hermes code to output the TX envelope PWM output for EER/ET: currently it's on the
io_lvds_txn
pin but any other available pin will be ok. Changes to the original Hermes files are minimal, mainly some name changes. Since the PWM needs a clock at 1024*240 kHz, 245.76 MHz, I've added a new output to the main PLL (clk_envelope
), doing a multiplication by 16/5 of the 76.8 MHz clock. ThePREDISTORTION
parameter has been removed and a newLRDATA
parameter added, that selects how the L/R downstream audio data are used. I had to change thelrdata
FIFO to use the same as for theiqdata
as the two streams need to remain in sync for EER.Unfortunately one thing still need to be fixed: there is a timing or initialization issue which sometimes causes the PWM output to toggle at the minimum duty cycle, as if it was not receiving the envelope data from the square root or FIR filter. After cycling power the PWM output may work properly.
Other minor things are in the notes of the files diffs below.