Open G7b9 opened 8 months ago
格式有些问题,#号被识别成title了,可以无视掉。应该只需要下面的op name
/model.22/cv4.0/cv4.0.2/Conv_output_0_Conv F32 /model.22/Mul_4_output_0_Mul F32 /model.22/Reshape_1_output_0_Reshape F32 /model.22/Add_1_output_0_Add F32 /model.22/cv4.1/cv4.1.0/conv/Conv_output_0_Conv F32 /model.22/cv4.1/cv4.1.1/conv/Conv_output_0_Conv F32 /model.22/Slice_3_output_0_Slice F32 /model.22/cv4.2/cv4.2.1/act/Mul_output_0_Mul F32 /model.22/Sub_1_output_0_Sub F32 /model.22/Mul_2_output_0_Mul F32 /model.22/Sigmoid_1_output_0_Sigmoid F32 /model.22/Concat_6_output_0_Concat F32 /model.22/cv4.1/cv4.1.2/Conv_output_0_Conv F32 /model.22/Add_3_output_0_Add F32 /model.22/Slice_output_0_Slice F32 /model.22/Concat_output_0_Concat F32 /model.22/Mul_3_output_0_Mul F32 /model.22/Div_1_output_0_Div F32 /model.22/cv4.0/cv4.0.1/conv/Conv_output_0_Conv F32 /model.22/dfl/conv/Conv_output_0_Conv F32 /model.22/cv4.1/cv4.1.0/act/Mul_output_0_Mul F32 /model.22/cv4.2/cv4.2.2/Conv_output_0_Conv F32 /model.22/dfl/Reshape_1_output_0_Reshape F32 /model.22/Slice_2_output_0_Slice F32 output0_Concat F32 /model.22/Reshape_2_output_0_Reshape F32 /model.22/Reshape_output_0_Reshape F32 /model.22/cv4.2/cv4.2.0/conv/Conv_output_0_Conv F32 /model.22/Add_2_output_0_Add F32 /model.22/cv4.2/cv4.2.0/act/Mul_output_0_Mul F32 /model.22/Slice_1_output_0_Slice F32 /model.22/cv4.2/cv4.2.1/conv/Conv_output_0_Conv F32 /model.22/cv4.0/cv4.0.0/conv/Conv_output_0_Conv F32 /model.22/cv4.0/cv4.0.1/act/Mul_output_0_Mul F32 /model.22/cv4.1/cv4.1.1/act/Mul_output_0_Mul F32 /model.22/Concat_5_output_0_Concat F32 /model.22/Sub_output_0_Sub F32 /model.22/Reshape_6_output_0_Reshape F32 /model.22/cv4.0/cv4.0.0/act/Mul_output_0_Mul F32 /model.22/Reshape_7_output_0_Reshape F32
好的,谢谢
v8s的能不能提供一个,谢谢
没做v8s的,参考着搞一下就可以了
格式有些问题,#号被识别成title了,可以无视掉。应该只需要下面的op name
genetated time: 2024-02-28 14:04:03.956377
chip: bm1684 mix_mode: F32
number of F32 layer: 40
op_name quantize_mode
/model.22/cv4.0/cv4.0.2/Conv_output_0_Conv F32 /model.22/Mul_4_output_0_Mul F32 /model.22/Reshape_1_output_0_Reshape F32 /model.22/Add_1_output_0_Add F32 /model.22/cv4.1/cv4.1.0/conv/Conv_output_0_Conv F32 /model.22/cv4.1/cv4.1.1/conv/Conv_output_0_Conv F32 /model.22/Slice_3_output_0_Slice F32 /model.22/cv4.2/cv4.2.1/act/Mul_output_0_Mul F32 /model.22/Sub_1_output_0_Sub F32 /model.22/Mul_2_output_0_Mul F32 /model.22/Sigmoid_1_output_0_Sigmoid F32 /model.22/Concat_6_output_0_Concat F32 /model.22/cv4.1/cv4.1.2/Conv_output_0_Conv F32 /model.22/Add_3_output_0_Add F32 /model.22/Slice_output_0_Slice F32 /model.22/Concat_output_0_Concat F32 /model.22/Mul_3_output_0_Mul F32 /model.22/Div_1_output_0_Div F32 /model.22/cv4.0/cv4.0.1/conv/Conv_output_0_Conv F32 /model.22/dfl/conv/Conv_output_0_Conv F32 /model.22/cv4.1/cv4.1.0/act/Mul_output_0_Mul F32 /model.22/cv4.2/cv4.2.2/Conv_output_0_Conv F32 /model.22/dfl/Reshape_1_output_0_Reshape F32 /model.22/Slice_2_output_0_Slice F32 output0_Concat F32 /model.22/Reshape_2_output_0_Reshape F32 /model.22/Reshape_output_0_Reshape F32 /model.22/cv4.2/cv4.2.0/conv/Conv_output_0_Conv F32 /model.22/Add_2_output_0_Add F32 /model.22/cv4.2/cv4.2.0/act/Mul_output_0_Mul F32 /model.22/Slice_1_output_0_Slice F32 /model.22/cv4.2/cv4.2.1/conv/Conv_output_0_Conv F32 /model.22/cv4.0/cv4.0.0/conv/Conv_output_0_Conv F32 /model.22/cv4.0/cv4.0.1/act/Mul_output_0_Mul F32 /model.22/cv4.1/cv4.1.1/act/Mul_output_0_Mul F32 /model.22/Concat_5_output_0_Concat F32 /model.22/Sub_output_0_Sub F32 /model.22/Reshape_6_output_0_Reshape F32 /model.22/cv4.0/cv4.0.0/act/Mul_output_0_Mul F32 /model.22/Reshape_7_output_0_Reshape F32