Memory model is weaker than we want

sorear / riscv-specs

UNOFFICIAL bug tracker for the RISC-V specifications

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Memory model is weaker than we want #4

Closed sorear closed 7 years ago

sorear commented 8 years ago

It's currently roughly Alpha, which nobody expects back, and has "interesting" implications for page zeroing on Linux and BSD kernels (NT should work fine because it still does zeroidle).

Foundation has expressed intent to strengthen it to roughly ARM/PowerPC level.

kasanovic commented 7 years ago

Foundation memory model task group has been spun up.