Closed lewispg228 closed 9 years ago
Can you please throw a test point on N$7 (by the vreg), I'd like to drop that line low with my testbed and verify the resistors are correct to switch between IOs.
Also, a TP on SIZE would be helpful for testing too.
thanks!
Good catches.
2) We talked about this at eng meeting. Not needed b/c ATmega can properly tri-state.
Everything else done. Two TPs added.
Sounds good. I'm not seeing your commits. Could you please double check that you pushed your changes?
I swear I hit the button at home. From work computer it shows changes. Not sure what's up. Should be committed now.
1) Make the silk "GND" now that it's grounded. It's currently "NC". Don't forget to update both top and bottom silk.
2) cool
Thanks for the test points, but you also created a 4-way node in the schematic.
Also, feel free to put test points directly over a via (and just approve the DRC errors). In fact, I prefer it, because it helps the pogopin center on the drill hit.
Good call. Fixed and committed.
1) On a lot of boards we have been grounding CTS on the FTDI header. Shouldn't this be grounded on this design too?
2) MISO tri-state buffer? Wanna talk to Grusin?
3) 3 GND flags should be symbols. Also, 2 gnd symbols off of left side of 328 should be orientated downward.
4) Use VCC symbol on VCC net off of U2
5) move designer name to tdocu
6) BLU and GRN text labels are lower than the rest, may as well get them lined up
7) 4 acid traps