FPGA Convolution (Im2col with aligned vectors and tiling)

[manuelburger]

Im2Col Convolution Implementation:

• 1D systolic array for GEMM
• reads/writes aligned vectors
• supports tiling
• supports arbitrary number of PEs for the systolic array
• buffers tile data to perform computation on unaligned vectors
• supports in-place relu activation

Xilinx:

• prefetch bias values to achieve II=1 pipelining in the writer processing element.

[codecov[bot]]

Codecov Report

Merging #79 (264ad0c) into master (c2133c6) will increase coverage by 0.19%. The diff coverage is 91.76%.

@@            Coverage Diff             @@
##           master      #79      +/-   ##
==========================================
+ Coverage   87.95%   88.14%   +0.19%     
==========================================
  Files          51       51              
  Lines        5312     5590     +278     
==========================================
+ Hits         4672     4927     +255     
- Misses        640      663      +23     

Impacted Files	Coverage Δ
...ml/onnx/op_implementations/fpga_implementations.py	90.59% <91.58%> (+0.33%)	:arrow_up:
daceml/onnx/nodes/onnx_op.py	94.24% <100.00%> (ø)
daceml/util/utils.py	91.74% <100.00%> (+0.36%)	:arrow_up:

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[manuelburger]

The CPU-CI failed due to test_training.py::test_bert[False]. This code is not at all related with that test. Also, that test passed for commit 55cd162 and fails now for commit 65df2ac, although nothing that has changed, should have an effect. Either the CI has some issues or there is a race condition in the training/bert code, I would guess.