spcl / gemm_hls

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.
BSD 3-Clause "New" or "Revised" License
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How to build GEMM on zcu102 platform #7

Closed yangjing69 closed 4 years ago

yangjing69 commented 5 years ago

Hi all, I tried to build gemm_hls on ZCU102 platform using SDx 2018.2. First, I modified the CMakeLists.txt which is in the gemm_hls-master project:

Target options

set(MM_PART_NAME "xczu9eg-ffvb1156-2-e" CACHE STRING "Part name for HLS.") set(MM_DSA_NAME "zcu102" CACHE STRING "DSA string for xocc.") set(MM_TARGET_CLOCK 250 CACHE STRING "Target clock for kernel (<=0 uses DSA default).") set(MM_TARGET_CLOCK_UNCERTAINTY 1.08 CACHE STRING "Clock uncertainty for HLS.")

Then, I compiled the gemm_hls-master, but something get wrong as below when I make link_hardware: cvg@cvg-XPS-8930:~/YJ/gemm_hls-master/build$ cmake ../ -- The C compiler identification is GNU 7.3.0 -- The CXX compiler identification is GNU 7.3.0 -- Check for working C compiler: /usr/bin/cc -- Check for working C compiler: /usr/bin/cc -- works -- Detecting C compiler ABI info -- Detecting C compiler ABI info - done -- Detecting C compile features -- Detecting C compile features - done -- Check for working CXX compiler: /usr/bin/c++ -- Check for working CXX compiler: /usr/bin/c++ -- works -- Detecting CXX compiler ABI info -- Detecting CXX compiler ABI info - done -- Detecting CXX compile features -- Detecting CXX compile features - done -- Looking for sys/types.h -- Looking for sys/types.h - found -- Looking for stdint.h -- Looking for stdint.h - found -- Looking for stddef.h -- Looking for stddef.h - found -- Check size of float -- Check size of float - done -- Found SDAccel: /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/xocc
-- Looking for include file pthread.h -- Looking for include file pthread.h - found -- Looking for pthread_create -- Looking for pthread_create - not found -- Looking for pthread_create in pthreads -- Looking for pthread_create in pthreads - not found -- Looking for pthread_create in pthread -- Looking for pthread_create in pthread - found -- Found Threads: TRUE
-- Configuring done -- Generating done -- Build files have been written to: /home/cvg/YJ/gemm_hls-master/build cvg@cvg-XPS-8930:~/YJ/gemm_hls-master/build$ make Scanning dependencies of target PrintSpecifications [ 11%] Building CXX object CMakeFiles/PrintSpecifications.dir/src/PrintSpecifications.cpp.o [ 22%] Linking CXX executable PrintSpecifications [ 22%] Built target PrintSpecifications Scanning dependencies of target mmkernel [ 33%] Building CXX object CMakeFiles/mmkernel.dir/kernel/Compute.cpp.o [ 44%] Building CXX object CMakeFiles/mmkernel.dir/kernel/Memory.cpp.o [ 55%] Linking CXX static library libmmkernel.a [ 55%] Built target mmkernel Scanning dependencies of target RunHardware.elf [ 66%] Building CXX object CMakeFiles/RunHardware.elf.dir/host/RunHardware.cpp.o [ 77%] Linking CXX executable RunHardware.elf [ 77%] Built target RunHardware.elf Scanning dependencies of target TestSimulation [ 88%] Building CXX object CMakeFiles/TestSimulation.dir/test/TestSimulation.cpp.o [100%] Linking CXX executable TestSimulation [100%] Built target TestSimulation cvg@cvg-XPS-8930:~/YJ/gemm_hls-master/build$ make synthesis Scanning dependencies of target synthesis

** Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2018.2 (64-bit) SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

source /media/cvg/DATA/ProgramFile/Vivado/2018.2/scripts/vivado_hls/hls.tcl -notrace INFO: [HLS 200-10] Running '/media/cvg/DATA/ProgramFile/Vivado/2018.2/bin/unwrapped/lnx64.o/vivado_hls' INFO: [HLS 200-10] For user 'cvg' on host 'cvg-XPS-8930' (Linux_x86_64 version 4.15.0-43-generic) on Wed Apr 10 13:29:08 CST 2019 INFO: [HLS 200-10] On os Ubuntu 18.04.1 LTS INFO: [HLS 200-10] In directory '/home/cvg/YJ/gemm_hls-master/build' INFO: [HLS 200-10] Creating and opening project '/home/cvg/YJ/gemm_hls-master/build/hls'. INFO: [HLS 200-10] Creating and opening solution '/home/cvg/YJ/gemm_hls-master/build/hls/xczu9eg-ffvb1156-2-i'. INFO: [HLS 200-10] Setting target device to 'xczu9eg-ffvb1156-2-i' INFO: [HLS 200-10] Adding design file '/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp' to the project INFO: [HLS 200-10] Adding design file '/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp' to the project INFO: [SYN 201-201] Setting up clock 'default' with a period of 4ns. INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 1.08ns. INFO: [XFORM 203-1171] Pipeline the innermost loop with trip count more than 64 or its parent loop when its trip count is less than or equal 64. INFO: [XFORM 203-1161] The maximum of name length is set into 256. INFO: [SCHED 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints. INFO: [HLS 200-10] Analyzing design file '/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp' ... WARNING: [HLS 214-114] Only function calls and local variable declarations are allowed in a dataflow region: /home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:301:25 INFO: [HLS 200-10] Analyzing design file '/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp' ... INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 375.648 ; gain = 0.098 ; free physical = 13004 ; free virtual = 16446 INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 375.648 ; gain = 0.098 ; free physical = 13004 ; free virtual = 16446 INFO: [HLS 200-10] Starting code transformations ... INFO: [XFORM 203-501] Unrolling loop 'Unroll_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:119) in function 'ProcessingElement(hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>&, hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>&, hlslib::Stream<hlslib::DataPack<float, 4>, 4u, (hlslib::Storage)0>&, hlslib::Stream<hlslib::DataPack<float, 4>, 4u, (hlslib::Storage)0>&, hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>&, hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>&, unsigned int, unsigned int, unsigned int, unsigned int)' completely. INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:23). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:90). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'ReadA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:107). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'ReadA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:113). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'TotalReadsFromA' (/home/cvg/YJ/gemm_hls-master/include/MatrixMultiplication.h:123). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'TransposeA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:172). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'TransposeA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:177). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'ReadB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:281). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'ReadB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:286). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'TotalReadsFromB' (/home/cvg/YJ/gemm_hls-master/include/MatrixMultiplication.h:131). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'WriteC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:378). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'WriteC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:382). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'FeedB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:413). INFO: [XFORM 203-603] Inlining function 'OuterTilesN' into 'FeedB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:417). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:23). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:90). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'ReadA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:107). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'ReadA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:115). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'TotalReadsFromA' (/home/cvg/YJ/gemm_hls-master/include/MatrixMultiplication.h:123). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'TransposeA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:172). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'TransposeA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:179). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'ReadB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:281). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'ReadB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:288). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'TotalReadsFromB' (/home/cvg/YJ/gemm_hls-master/include/MatrixMultiplication.h:131). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'WriteC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:378). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'WriteC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:384). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'FeedB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:413). INFO: [XFORM 203-603] Inlining function 'OuterTilesM' into 'FeedB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:418). INFO: [XFORM 203-603] Inlining function 'TotalReadsFromA' into 'ReadA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:107). INFO: [XFORM 203-603] Inlining function 'TotalReadsFromA' into 'TransposeA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:172). INFO: [XFORM 203-603] Inlining function 'SizeKMemory' into 'IndexA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:17). INFO: [XFORM 203-603] Inlining function 'SizeKMemory' into 'IndexA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:19). INFO: [XFORM 203-603] Inlining function 'IndexA' into '_ReadAInner' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:65). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 16>::operator[]' into 'ConvertWidthC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:362). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 16>::operator[]' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:332). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 16>::operator[]' into '_ReadAInner' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:69). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 16>::Get' into 'hlslib::(anonymous namespace)::DataPackProxy<float, 16>::operator float' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:227). INFO: [XFORM 203-603] Inlining function 'hlslib::(anonymous namespace)::DataPackProxy<float, 16>::operator float' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:332). INFO: [XFORM 203-603] Inlining function 'hlslib::(anonymous namespace)::DataPackProxy<float, 16>::operator float' into '_ReadAInner' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:69). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<float, 512u, (hlslib::Storage)0>::WriteBlocking.1' into 'hlslib::Stream<float, 512u, (hlslib::Storage)0>::WriteBlocking' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<float, 512u, (hlslib::Storage)0>::WriteBlocking' into 'hlslib::Stream<float, 512u, (hlslib::Storage)0>::Push' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<float, 512u, (hlslib::Storage)0>::Push' into '_ReadAInner' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:69). INFO: [XFORM 203-603] Inlining function '_ReadAInner' into '_ReadAInnerLoop<1u>' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:99). INFO: [XFORM 203-603] Inlining function '_ReadAInnerLoop<1u>' into 'ReadA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:122). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 1>::operator[].1' into '_TransposeAInner<1u>' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:160). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<float, 512u, (hlslib::Storage)0>::ReadBlocking' into 'hlslib::Stream<float, 512u, (hlslib::Storage)0>::Pop' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:284). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<float, 512u, (hlslib::Storage)0>::Pop' into '_TransposeAInner<1u>' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:160). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 1>::Set' into 'hlslib::(anonymous namespace)::DataPackProxy<float, 1>::operator=' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:212). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::WriteBlocking.1' into 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::WriteBlocking' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::WriteBlocking' into 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::Push' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::Push' into '_TransposeAInner<1u>' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:161). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::Push' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:104). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::Push' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:52). INFO: [XFORM 203-603] Inlining function '_TransposeAInner<1u>' into 'TransposeA' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:182). INFO: [XFORM 203-603] Inlining function 'TotalReadsFromB' into 'ReadB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:281). INFO: [XFORM 203-603] Inlining function 'TotalReadsFromB' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:310). INFO: [XFORM 203-603] Inlining function 'TotalReadsFromB' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:310). INFO: [XFORM 203-603] Inlining function 'TotalReadsFromB' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:313). INFO: [XFORM 203-603] Inlining function 'TotalReadsFromB' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:313). INFO: [XFORM 203-603] Inlining function 'TotalReadsFromB' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:319). INFO: [XFORM 203-603] Inlining function 'TotalReadsFromB' into 'FeedB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:413). INFO: [XFORM 203-603] Inlining function 'SizeMMemory' into 'IndexB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:42). INFO: [XFORM 203-603] Inlining function 'SizeMMemory' into 'IndexB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:43). INFO: [XFORM 203-603] Inlining function 'SizeMMemory' into 'IndexC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:51). INFO: [XFORM 203-603] Inlining function 'SizeMMemory' into 'IndexC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:53). INFO: [XFORM 203-603] Inlining function 'IndexB' into 'ReadB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:296). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 16>, 32u, (hlslib::Storage)0>::WriteBlocking.1' into 'hlslib::Stream<hlslib::DataPack<float, 16>, 32u, (hlslib::Storage)0>::WriteBlocking' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 16>, 32u, (hlslib::Storage)0>::WriteBlocking' into 'hlslib::Stream<hlslib::DataPack<float, 16>, 32u, (hlslib::Storage)0>::Push' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 16>, 32u, (hlslib::Storage)0>::Push' into 'ConvertWidthC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:365). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 16>, 32u, (hlslib::Storage)0>::Push' into 'ReadB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:296). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 16>, 32u, (hlslib::Storage)0>::ReadBlocking' into 'hlslib::Stream<hlslib::DataPack<float, 16>, 32u, (hlslib::Storage)0>::Pop' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:284). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 16>, 32u, (hlslib::Storage)0>::Pop' into 'WriteC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:391). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 16>, 32u, (hlslib::Storage)0>::Pop' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:326). INFO: [XFORM 203-603] Inlining function '_ZN6hlslib12_GLOBAL__N_113DataPackProxyIfLi4EEC2ERNS_8DataPackIfLi4EEEi80' into '_ZN6hlslib8DataPackIfLi4EEixEm72' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:242). INFO: [XFORM 203-603] Inlining function '_ZN6hlslib8DataPackIfLi4EEixEm72' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:332). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 4>::Set' into 'hlslib::(anonymous namespace)::DataPackProxy<float, 4>::operator=.1' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:212). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 4>::Set' into 'hlslib::DataPack<float, 4>::Fill' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:104). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 4>::Set' into 'hlslib::(anonymous namespace)::DataPackProxy<float, 4>::operator=' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:207). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::WriteBlocking.1' into 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::WriteBlocking' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::WriteBlocking' into 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::Push' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::Push' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:334). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::Push' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:182). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::Push' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:169). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::ReadBlocking' into 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::Pop' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:284). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::Pop' into 'FeedB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:437). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::Pop' into 'ConvertWidthC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:358). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 1u, (hlslib::Storage)0>::Pop' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:182). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 4u, (hlslib::Storage)0>::WriteBlocking.1' into 'hlslib::Stream<hlslib::DataPack<float, 4>, 4u, (hlslib::Storage)0>::WriteBlocking' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 4u, (hlslib::Storage)0>::WriteBlocking' into 'hlslib::Stream<hlslib::DataPack<float, 4>, 4u, (hlslib::Storage)0>::Push' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 4u, (hlslib::Storage)0>::Push' into 'FeedB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:442). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 4u, (hlslib::Storage)0>::Push' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:115). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::ReadBlocking' into 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::Pop' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:284). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::Pop' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:94). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::Pop' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:59). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 1>, 4u, (hlslib::Storage)0>::Pop' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:48). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 4u, (hlslib::Storage)0>::ReadBlocking' into 'hlslib::Stream<hlslib::DataPack<float, 4>, 4u, (hlslib::Storage)0>::Pop' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:284). INFO: [XFORM 203-603] Inlining function 'hlslib::Stream<hlslib::DataPack<float, 4>, 4u, (hlslib::Storage)0>::Pop' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:113). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 4>::Fill' into 'hlslib::DataPack<float, 4>::DataPack.2' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:46). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 1>::Get' into 'hlslib::DataPack<float, 1>::operator[]' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:150). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 1>::operator[]' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:131). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 4>::Get' into 'hlslib::DataPack<float, 4>::operator[]' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:150). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 4>::operator[]' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:133). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 4>::operator[]' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:131). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 4>::operator[]' into 'ConvertWidthC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:362). INFO: [XFORM 203-603] Inlining function 'hlslib::op::Product::Apply<float, float>' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:131). INFO: [XFORM 203-603] Inlining function 'hlslib::op::Sum::Apply<float const&, float const&>' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:135). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 4>::operator[].1' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:137). INFO: [XFORM 203-603] Inlining function 'hlslib::DataPack<float, 16>::Set' into 'hlslib::(anonymous namespace)::DataPackProxy<float, 16>::operator=' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:212). INFO: [XFORM 203-603] Inlining function 'IndexC' into 'WriteC' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:391). INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:17 ; elapsed = 00:00:19 . Memory (MB): peak = 504.344 ; gain = 128.793 ; free physical = 12980 ; free virtual = 16424 INFO: [HLS 200-10] Checking synthesizability ... INFO: [XFORM 203-602] Inlining function 'std::numeric_limits::max' into 'ReadA' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380->/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392->/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:69->/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:99->/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:122) automatically. INFO: [XFORM 203-602] Inlining function 'std::numeric_limits::max' into 'TransposeA' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380->/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392->/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:161->/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:182) automatically. INFO: [XFORM 203-602] Inlining function 'std::numeric_limits::max' into 'ReadB' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380->/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392->/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:296) automatically. INFO: [XFORM 203-602] Inlining function '_ZN6hlslib12_GLOBAL__N_113DataPackProxyIfLi4EED2Ev79' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:332) automatically. INFO: [XFORM 203-602] Inlining function 'std::numeric_limits::max' into 'ConvertWidthB' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380->/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392->/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:334) automatically. INFO: [XFORM 203-602] Inlining function 'std::numeric_limits::max' into 'FeedB' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380->/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392->/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:442) automatically. INFO: [XFORM 203-602] Inlining function 'std::numeric_limits::max' into 'ProcessingElement' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380->/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392->/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:52) automatically. INFO: [XFORM 203-602] Inlining function 'std::numeric_limits::max' into 'ConvertWidthC' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:380->/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:392->/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:365) automatically. WARNING: [SYNCHK 200-23] /home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:82: variable-indexed range selection may cause suboptimal QoR. INFO: [SYNCHK 200-10] 0 error(s), 1 warning(s). INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 504.344 ; gain = 128.793 ; free physical = 12964 ; free virtual = 16410 INFO: [XFORM 203-510] Pipelining loop 'ReadA_N2' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:121) in function 'ReadA' automatically. INFO: [XFORM 203-510] Pipelining loop 'Loop-2' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:278) in function 'MatrixMultiplicationKernel' automatically. INFO: [XFORM 203-510] Pipelining loop 'Loop-3' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:281) in function 'MatrixMultiplicationKernel' automatically. INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'ConvertWidthB_Memory' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:322) in function 'ConvertWidthB' for pipelining. INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Loop-1.1' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:355) in function 'ConvertWidthC' for pipelining. INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'ReadA_N2' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:121) in function 'ReadA' for pipelining. INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41) in function 'ProcessingElement' for pipelining. INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Pipeline_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77) in function 'ProcessingElement' for pipelining. INFO: [XFORM 203-501] Unrolling loop 'Loop-3' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:331) in function 'MatrixMultiplicationKernel' completely. INFO: [XFORM 203-501] Unrolling loop 'ConvertWidthB_Compute' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:330) in function 'ConvertWidthB' completely. INFO: [XFORM 203-501] Unrolling loop 'ConvertWidthB_Compute' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:360) in function 'ConvertWidthC' completely. INFO: [XFORM 203-501] Unrolling loop 'ReadA_Unroll' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:67) in function 'ReadA' completely. WARNING: [XFORM 203-503] Cannot unroll loop 'InitializeABuffer_Outer' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:45) in function 'ProcessingElement': cannot completely unroll a loop with a variable trip count. INFO: [XFORM 203-501] Unrolling loop 'DataPack_Fill' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:102) in function 'ProcessingElement' completely. INFO: [XFORM 203-501] Unrolling loop 'Unroll_M' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:128) in function 'ProcessingElement' completely. INFO: [XFORM 203-102] Automatically partitioning streamed array 'aSplit' . INFO: [XFORM 203-102] Automatically partitioning streamed array 'aPipes.stream.V.data.V' . INFO: [XFORM 203-102] Automatically partitioning streamed array 'bPipes.stream.V.data.V' . INFO: [XFORM 203-102] Automatically partitioning streamed array 'cPipes.stream.V.data.V' . INFO: [XFORM 203-101] Partitioning array 'cBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36) in dimension 2 completely. INFO: [XFORM 203-101] Partitioning array 'aSplit' in dimension 1 completely. INFO: [XFORM 203-101] Partitioning array 'aPipes.stream.V.data.V' in dimension 1 completely. INFO: [XFORM 203-101] Partitioning array 'bPipes.stream.V.data.V' in dimension 1 completely. INFO: [XFORM 203-101] Partitioning array 'cPipes.stream.V.data_.V' in dimension 1 completely. INFO: [XFORM 203-721] Changing loop 'Loop_1_proc' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:278) to a process function for dataflow in function 'MatrixMultiplicationKernel'. INFO: [XFORM 203-721] Changing loop 'Loop_2_proc' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:281) to a process function for dataflow in function 'MatrixMultiplicationKernel'. INFO: [XFORM 203-712] Applying dataflow to function 'MatrixMultiplicationKernel', detected/extracted 25 process function(s): 'Loop_1_proc' 'Loop_2_proc' 'ReadA' 'TransposeA' 'ReadB' 'ConvertWidthB' 'FeedB' 'ProcessingElement87' 'ProcessingElement88' 'ProcessingElement89' 'ProcessingElement90' 'ProcessingElement91' 'ProcessingElement92' 'ProcessingElement93' 'ProcessingElement94' 'ProcessingElement95' 'ProcessingElement96' 'ProcessingElement97' 'ProcessingElement98' 'ProcessingElement99' 'ProcessingElement100' 'ProcessingElement101' 'ProcessingElement102' 'ConvertWidthC' 'WriteC'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 4 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement99'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 4 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement99'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 5 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement98'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 5 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement98'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 6 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement97'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 6 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement97'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 7 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement96'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 7 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement96'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 8 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement95'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 8 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement95'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 9 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement94'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 9 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement94'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 10 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement93'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 10 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement93'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 11 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement92'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 11 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement92'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 12 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement91'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 12 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement91'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 13 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement90'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 13 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement90'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 14 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement89'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 14 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement89'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 15 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement88'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 15 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement88'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 16 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement87'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 2 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement101'. WARNING: [XFORM 203-561] Updating loop upper bound from 16 to 3 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement100'. WARNING: [XFORM 203-561] Updating loop lower bound from 2 to 3 for loop 'InitializeABuffer_Outer' in function 'ProcessingElement100'. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement99'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement98'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement97'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement96'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement95'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement94'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement93'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement92'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement91'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement90'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement89'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement88'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement87'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement102'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement101'... converting 3 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:111:76) to (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:77:52) in function 'ProcessingElement100'... converting 3 basic blocks. INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 504.344 ; gain = 128.793 ; free physical = 12922 ; free virtual = 16371 INFO: [XFORM 203-541] Flattening a loop nest 'WriteC_N1' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:386:58) in function 'WriteC'. INFO: [XFORM 203-541] Flattening a loop nest 'WriteC_OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:384:60) in function 'WriteC'. INFO: [XFORM 203-541] Flattening a loop nest 'WriteC_OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:382:58) in function 'WriteC'. INFO: [XFORM 203-541] Flattening a loop nest 'TransposeA_K' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:181:46) in function 'TransposeA'. INFO: [XFORM 203-541] Flattening a loop nest 'TransposeA_M0' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:179:60) in function 'TransposeA'. INFO: [XFORM 203-541] Flattening a loop nest 'TransposeA_N0' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:177:58) in function 'TransposeA'. INFO: [XFORM 203-541] Flattening a loop nest 'ReadB_K' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:290:46) in function 'ReadB'. INFO: [XFORM 203-541] Flattening a loop nest 'ReadB_OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:288:60) in function 'ReadB'. INFO: [XFORM 203-541] Flattening a loop nest 'ReadB_OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:286:58) in function 'ReadB'. INFO: [XFORM 203-541] Flattening a loop nest 'ReadA_N1' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:119:57) in function 'ReadA'. INFO: [XFORM 203-541] Flattening a loop nest 'ReadA_K0' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:117:67) in function 'ReadA'. INFO: [XFORM 203-541] Flattening a loop nest 'ReadA_M0' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:115:60) in function 'ReadA'. INFO: [XFORM 203-541] Flattening a loop nest 'ReadA_N0' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:113:58) in function 'ReadA'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement99'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement99'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement99'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement99' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement99'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement98'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement98'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement98'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement98' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement98'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement97'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement97'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement97'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement97' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement97'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement96'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement96'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement96'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement96' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement96'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement95'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement95'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement95'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement95' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement95'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement94'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement94'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement94'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement94' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement94'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement93'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement93'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement93'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement93' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement93'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement92'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement92'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement92'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement92' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement92'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement91'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement91'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement91'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement91' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement91'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement90'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement90'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement90'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement90' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement90'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement89'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement89'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement89'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement89' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement89'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement88'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement88'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement88'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement88' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement88'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement87'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement87'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement87'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement87' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement87'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement102'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement102'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement102' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement102'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement101'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement101'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement101'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement101' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement101'. INFO: [XFORM 203-541] Flattening a loop nest 'InitializeABuffer_Inner' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:41:51) in function 'ProcessingElement100'. INFO: [XFORM 203-541] Flattening a loop nest 'Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:74:57) in function 'ProcessingElement100'. INFO: [XFORM 203-541] Flattening a loop nest 'Collapse_K' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:70:46) in function 'ProcessingElement100'. WARNING: [XFORM 203-542] Cannot flatten a loop nest 'OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:66:60) in function 'ProcessingElement100' :

more than one sub loop. INFO: [XFORM 203-541] Flattening a loop nest 'OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp:64:58) in function 'ProcessingElement100'. INFO: [XFORM 203-541] Flattening a loop nest 'FeedB_Pipeline_N' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:430:57) in function 'FeedB'. INFO: [XFORM 203-541] Flattening a loop nest 'FeedB_K' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:425:46) in function 'FeedB'. INFO: [XFORM 203-541] Flattening a loop nest 'FeedB_OuterTile_M' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:423:48) in function 'FeedB'. INFO: [XFORM 203-541] Flattening a loop nest 'FeedB_OuterTile_N' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:421:46) in function 'FeedB'. INFO: [XFORM 203-541] Flattening a loop nest 'ConvertWidthC_Outer' (/home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp:351:77) in function 'ConvertWidthC'. INFO: [XFORM 203-541] Flattening a loop nest 'ConvertWidthB_Outer' (/home/cvg/YJ/gemmhls-master/kernel/Memory.cpp:319:75) in function 'ConvertWidthB'. WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'aBuffer.data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:33). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'cBuffer[0].data.V' (/home/cvg/YJ/gemmhls-master/kernel/Compute.cpp:36). INFO: [XFORM 203-811] Inferring multiple bus burst write of a total cumulative length 16 on port 'memory.data.V' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/DataPack.h:56:2). These data requests might be further partitioned to multiple requests during RTL generation, based on max_read_burst_length or max_write_burstlength settings. INFO: [XFORM 203-811] Inferring multiple bus burst read of a total cumulative length 16 on port 'memory.data.V' (/home/cvg/YJ/gemm_hls-master/hlslib/include/hlslib/xilinx/Stream.h:343:2). These data requests might be further partitioned to multiple requests during RTL generation, based on max_read_burst_length or max_write_burst_length settings. INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:00:26 ; elapsed = 00:00:27 . Memory (MB): peak = 717.754 ; gain = 342.203 ; free physical = 12696 ; free virtual = 16145 INFO: [HLS 200-10] Starting hardware synthesis ... INFO: [HLS 200-10] Synthesizing 'MatrixMultiplicationKernel' ... WARNING: [SYN 201-103] Legalizing function name 'MatrixMultiplicationKernel.entry6' to 'MatrixMultiplicationKernel_entry6'. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'MatrixMultiplicationKernel_entry6' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 27.25 seconds; current allocated memory: 376.095 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.01 seconds; current allocated memory: 376.171 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ReadA' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'ReadA_N0_ReadA_K0_ReadA_N1_ReadA_N2'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 12. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.29 seconds; current allocated memory: 376.821 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.11 seconds; current allocated memory: 377.685 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'TransposeA' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'TransposeA_N0_TransposeA_K_L'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.37 seconds; current allocated memory: 378.288 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.06 seconds; current allocated memory: 378.732 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ReadB' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'ReadB_OuterTile_N_ReadB_K_ReadB_BufferB_M1'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 11. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.14 seconds; current allocated memory: 379.156 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.07 seconds; current allocated memory: 379.553 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ConvertWidthB' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'ConvertWidthB_Outer_ConvertWidthB_Memory'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.16 seconds; current allocated memory: 380.083 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.07 seconds; current allocated memory: 380.480 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'FeedB' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'FeedB_OuterTile_N_FeedB_K_FeedB_Pipeline_N_FeedB_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.15 seconds; current allocated memory: 380.899 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.06 seconds; current allocated memory: 381.195 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement87' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.34 seconds; current allocated memory: 382.371 MB. INFO: [HLS 200-434] Only 3 loops out of a total 4 loops have been pipelined in this design. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.22 seconds; current allocated memory: 383.464 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement88' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.44 seconds; current allocated memory: 384.537 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.2 seconds; current allocated memory: 385.570 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement89' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.45 seconds; current allocated memory: 386.682 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.2 seconds; current allocated memory: 387.745 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement90' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.45 seconds; current allocated memory: 388.823 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.2 seconds; current allocated memory: 389.852 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement91' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.45 seconds; current allocated memory: 390.949 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.2 seconds; current allocated memory: 392.013 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement92' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.45 seconds; current allocated memory: 393.098 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.2 seconds; current allocated memory: 394.123 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement93' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.46 seconds; current allocated memory: 395.217 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.21 seconds; current allocated memory: 396.280 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement94' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.46 seconds; current allocated memory: 397.375 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.2 seconds; current allocated memory: 398.402 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement95' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.46 seconds; current allocated memory: 399.484 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.21 seconds; current allocated memory: 400.552 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement96' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.46 seconds; current allocated memory: 401.629 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.21 seconds; current allocated memory: 402.666 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement97' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.46 seconds; current allocated memory: 403.782 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.21 seconds; current allocated memory: 404.803 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement98' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.46 seconds; current allocated memory: 405.894 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.2 seconds; current allocated memory: 406.919 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement99' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.46 seconds; current allocated memory: 408.048 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.21 seconds; current allocated memory: 409.072 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement100' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.46 seconds; current allocated memory: 410.164 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.21 seconds; current allocated memory: 411.189 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement101' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.46 seconds; current allocated memory: 412.303 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.21 seconds; current allocated memory: 413.327 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ProcessingElement102' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'InitializeABuffer_Inner'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [SCHED 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.4 seconds; current allocated memory: 414.316 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.19 seconds; current allocated memory: 415.261 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'ConvertWidthC' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'ConvertWidthC_Outer_L'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.3 seconds; current allocated memory: 415.913 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.09 seconds; current allocated memory: 416.414 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'WriteC' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining loop 'WriteC_OuterTile_N_WriteC_N1_WriteC_M1'. INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 10. INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.19 seconds; current allocated memory: 416.973 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 0.08 seconds; current allocated memory: 417.403 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'MatrixMultiplicationKernel' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Elapsed time: 0.15 seconds; current allocated memory: 418.011 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Elapsed time: 4.05 seconds; current allocated memory: 423.670 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'MatrixMultiplicationKernel_entry6' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'MatrixMultiplicationKernel_entry6'. INFO: [HLS 200-111] Elapsed time: 1.7 seconds; current allocated memory: 425.516 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ReadA' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'ReadA'. INFO: [HLS 200-111] Elapsed time: 0.07 seconds; current allocated memory: 426.959 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'TransposeA' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'TransposeA'. INFO: [HLS 200-111] Elapsed time: 0.28 seconds; current allocated memory: 430.436 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ReadB' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'ReadB'. INFO: [HLS 200-111] Elapsed time: 0.21 seconds; current allocated memory: 432.862 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ConvertWidthB' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'ConvertWidthB'. INFO: [HLS 200-111] Elapsed time: 0.2 seconds; current allocated memory: 435.006 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'FeedB' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'FeedB'. INFO: [HLS 200-111] Elapsed time: 0.24 seconds; current allocated memory: 437.427 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement87' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement87'. INFO: [HLS 200-111] Elapsed time: 0.26 seconds; current allocated memory: 440.776 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement88' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement88'. INFO: [HLS 200-111] Elapsed time: 0.55 seconds; current allocated memory: 446.286 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement89' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement89'. INFO: [HLS 200-111] Elapsed time: 0.57 seconds; current allocated memory: 452.185 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement90' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement90'. INFO: [HLS 200-111] Elapsed time: 0.57 seconds; current allocated memory: 457.850 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement91' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement91'. INFO: [HLS 200-111] Elapsed time: 0.62 seconds; current allocated memory: 463.473 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement92' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement92'. INFO: [HLS 200-111] Elapsed time: 0.6 seconds; current allocated memory: 469.069 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement93' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement93'. INFO: [HLS 200-111] Elapsed time: 0.62 seconds; current allocated memory: 474.683 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement94' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement94'. INFO: [HLS 200-111] Elapsed time: 0.63 seconds; current allocated memory: 480.829 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement95' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement95'. INFO: [HLS 200-111] Elapsed time: 0.65 seconds; current allocated memory: 486.449 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement96' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement96'. INFO: [HLS 200-111] Elapsed time: 0.66 seconds; current allocated memory: 492.042 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement97' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement97'. INFO: [HLS 200-111] Elapsed time: 0.67 seconds; current allocated memory: 497.657 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement98' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement98'. INFO: [HLS 200-111] Elapsed time: 0.68 seconds; current allocated memory: 503.268 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement99' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement99'. INFO: [HLS 200-111] Elapsed time: 0.7 seconds; current allocated memory: 508.876 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement100' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement100'. INFO: [HLS 200-111] Elapsed time: 0.71 seconds; current allocated memory: 514.422 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement101' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement101'. INFO: [HLS 200-111] Elapsed time: 0.72 seconds; current allocated memory: 520.034 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ProcessingElement102' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fadd_32ns_32ns_32_10_full_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Generating core module 'MatrixMultiplicationKernel_fmul_32ns_32ns_32_6_max_dsp_1': 4 instance(s). INFO: [RTGEN 206-100] Finished creating RTL model for 'ProcessingElement102'. INFO: [HLS 200-111] Elapsed time: 0.72 seconds; current allocated memory: 525.508 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'ConvertWidthC' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'ConvertWidthC'. INFO: [HLS 200-111] Elapsed time: 0.7 seconds; current allocated memory: 529.783 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'WriteC' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-100] Finished creating RTL model for 'WriteC'. INFO: [HLS 200-111] Elapsed time: 0.49 seconds; current allocated memory: 532.933 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'MatrixMultiplicationKernel' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [RTGEN 206-500] Setting interface mode on port 'MatrixMultiplicationKernel/gmem0' to 'm_axi'. INFO: [RTGEN 206-500] Setting interface mode on port 'MatrixMultiplicationKernel/gmem1' to 'm_axi'. INFO: [RTGEN 206-500] Setting interface mode on port 'MatrixMultiplicationKernel/gmem2' to 'm_axi'. INFO: [RTGEN 206-500] Setting interface mode on port 'MatrixMultiplicationKernel/a_data_V' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'MatrixMultiplicationKernel/b_data_V' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'MatrixMultiplicationKernel/c_data_V' to 's_axilite & ap_none'. INFO: [RTGEN 206-500] Setting interface mode on function 'MatrixMultiplicationKernel' to 's_axilite & ap_ctrl_hs'. INFO: [RTGEN 206-100] Bundling port 'return', 'a_data_V', 'b_data_V' and 'c_data_V' to AXI-Lite port control. INFO: [RTGEN 206-100] Finished creating RTL model for 'MatrixMultiplicationKernel'. INFO: [HLS 200-111] Elapsed time: 0.58 seconds; current allocated memory: 539.694 MB. INFO: [RTMG 210-278] Implementing memory 'FeedB_buffer_data_V_ram (RAM)' using block RAMs. INFO: [RTMG 210-278] Implementing memory 'ProcessingElement87_aBuffer_data_V_ram (RAM)' using block RAMs. INFO: [RTMG 210-278] Implementing memory 'ProcessingElement87_cBuffer_0_data_V_ram (RAM)' using block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'a_data_V_c_U(fifo_w64_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'b_data_V_c_U(fifo_w64_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'c_data_V_c_U(fifo_w64_d7_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_0_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_1_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_2_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_3_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_4_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_5_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_6_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_7_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_8_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_9_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_10_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_11_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_12_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_13_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_14_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aSplit_15_U(fifo_w32_d512_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_0_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bMemory_stream_V_data_V_U(fifo_w512_d32_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_0_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_1_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_1_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_2_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_2_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_3_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_3_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_4_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_4_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_5_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_5_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_6_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_6_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_7_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_7_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_8_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_8_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_9_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_9_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_10_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_10_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_11_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_11_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_12_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_12_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_13_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_13_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_14_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_14_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'aPipes_stream_V_data_V_15_U(fifo_w32_d2_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'bPipes_stream_V_data_V_15_U(fifo_w128_d4_A)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'cMemory_stream_V_data_V_U(fifo_w512_d32_A)' using Block RAMs. INFO: [RTMG 210-285] Implementing FIFO 'start_for_WriteC_U0_U(start_for_WriteC_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_TransposeA_U0_U(start_for_TransposeA_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement87_U0_U(start_for_ProcessingElement87_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ConvertWidthB_U0_U(start_for_ConvertWidthB_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_FeedB_U0_U(start_for_FeedB_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement88_U0_U(start_for_ProcessingElement88_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ConvertWidthC_U0_U(start_for_ConvertWidthC_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement89_U0_U(start_for_ProcessingElement89_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement90_U0_U(start_for_ProcessingElement90_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement91_U0_U(start_for_ProcessingElement91_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement92_U0_U(start_for_ProcessingElement92_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement93_U0_U(start_for_ProcessingElement93_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement94_U0_U(start_for_ProcessingElement94_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement95_U0_U(start_for_ProcessingElement95_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement96_U0_U(start_for_ProcessingElement96_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement97_U0_U(start_for_ProcessingElement97_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement98_U0_U(start_for_ProcessingElement98_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement99_U0_U(start_for_ProcessingElement99_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement100_U0_U(start_for_ProcessingElement100_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement101_U0_U(start_for_ProcessingElement101_U0)' using Shift Registers. INFO: [RTMG 210-285] Implementing FIFO 'start_for_ProcessingElement102_U0_U(start_for_ProcessingElement102_U0)' using Shift Registers. INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:00:57 ; elapsed = 00:01:04 . Memory (MB): peak = 973.973 ; gain = 598.422 ; free physical = 12431 ; free virtual = 15960 INFO: [SYSC 207-301] Generating SystemC RTL for MatrixMultiplicationKernel. INFO: [VHDL 208-304] Generating VHDL RTL for MatrixMultiplicationKernel. INFO: [VLOG 209-307] Generating Verilog RTL for MatrixMultiplicationKernel. INFO: [HLS 200-112] Total elapsed time: 64.4 seconds; peak allocated memory: 539.694 MB. INFO: [Common 17-206] Exiting vivado_hls at Wed Apr 10 13:30:12 2019... Built target synthesis cvg@cvg-XPS-8930:~/YJ/gemm_hls-master/build$ make compile_hardware Scanning dependencies of target compile_hardware

** xocc v2018.2 (64-bit) ** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: ap_opencl WARNING: [XOCC 17-301] Failed to get a license for 'ap_opencl'. Explanation: The license feature ap_opencl could not be found. Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". Attempting to get a license: ap_sdsoc Feature available: ap_sdsoc INFO: [XOCC 60-585] Compiling for hardware target Running SDx Rule Check Server on port:34001 INFO: [XOCC 60-895] Target platform: /media/cvg/DATA/ProgramFile/SDx/2018.2/platforms/zcu102/zcu102.xpfm INFO: [XOCC 60-423] Target device: zcu102 INFO: [XOCC 60-242] Creating kernel: 'MatrixMultiplicationKernel'

===>The following messages were generated while performing high-level synthesis for kernel: MatrixMultiplicationKernel Log file:/home/cvg/YJ/gemm_hls-master/build/_x/MatrixMultiplication_hw/MatrixMultiplicationKernel/vivado_hls.log : INFO: [XOCC 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints. INFO: [XOCC 204-61] Pipelining loop 'ReadA_N0_ReadA_K0_ReadA_N1_ReadA_N2'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 12. INFO: [XOCC 204-61] Pipelining loop 'TransposeA_N0_TransposeA_K_L'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4. INFO: [XOCC 204-61] Pipelining loop 'ReadB_OuterTile_N_ReadB_K_ReadB_BufferB_M1'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 11. INFO: [XOCC 204-61] Pipelining loop 'ConvertWidthB_Outer_ConvertWidthB_Memory'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4. INFO: [XOCC 204-61] Pipelining loop 'FeedB_OuterTile_N_FeedB_K_FeedB_Pipeline_N_FeedB_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 17-14] Message 'XOCC 204-61' appears 100 times and further instances of the messages will be disabled. INFO: [XOCC 60-594] Finished kernel compilation INFO: [XOCC 60-244] Generating system estimate report... INFO: [XOCC 60-1092] Generated system estimate report: /home/cvg/YJ/gemm_hls-master/build/_x/reports/MatrixMultiplication_hw/system_estimate_MatrixMultiplication_hw.xtxt Add Instance ConvertWidthC ConvertWidthC_U0 552 Add Instance ConvertWidthB ConvertWidthB_U0 558 Add Instance ProcessingElement87 ProcessingElement87_U0 564 Add Instance ProcessingElement89 ProcessingElement89_U0 574 Add Instance ProcessingElement91 ProcessingElement91_U0 584 Add Instance ProcessingElement88 ProcessingElement88_U0 594 Add Instance ProcessingElement90 ProcessingElement90_U0 604 Add Instance ProcessingElement92 ProcessingElement92_U0 614 Add Instance ProcessingElement93 ProcessingElement93_U0 624 Add Instance ProcessingElement94 ProcessingElement94_U0 634 Add Instance ProcessingElement95 ProcessingElement95_U0 644 Add Instance ProcessingElement96 ProcessingElement96_U0 654 Add Instance ProcessingElement97 ProcessingElement97_U0 664 Add Instance ProcessingElement98 ProcessingElement98_U0 674 Add Instance ProcessingElement99 ProcessingElement99_U0 684 Add Instance ProcessingElement100 ProcessingElement100_U0 694 Add Instance ProcessingElement101 ProcessingElement101_U0 704 Add Instance ProcessingElement102 ProcessingElement102_U0 714 Add Instance ReadA ReadA_U0 721 Add Instance WriteC WriteC_U0 744 Add Instance ReadB ReadB_U0 752 Add Instance TransposeA TransposeA_U0 760 Add Instance FeedB FeedB_U0 781 Add Instance MatrixMultiplicationKernel_entry6 MatrixMultiplicationKernel_entry6_U0 787 INFO: [XOCC 60-586] Created MatrixMultiplication_hw.xo INFO: [XOCC 60-791] Total elapsed time: 0h 1m 48s Built target compile_hardware cvg@cvg-XPS-8930:~/YJ/gemm_hls-master/build$ make link_hardware Scanning dependencies of target link_hardware

** xocc v2018.2 (64-bit) ** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

INFO: [XOCC 60-629] Linking for hardware target Running SDx Rule Check Server on port:43689 INFO: [XOCC 60-895] Target platform: /media/cvg/DATA/ProgramFile/SDx/2018.2/platforms/zcu102/zcu102.xpfm INFO: [XOCC 60-423] Target device: zcu102 WARNING: [XOCC 60-887] No System Configuration (--sys_config) option was specified for XOCC Link. A system boot image will not be generated. The current Platform has the following System Configurations: 'a53_linux', 'a53_standalone', 'ocl', 'r5_standalone' INFO: [XOCC 60-825] xocc command line options for sdx_link are --xo MatrixMultiplication_hw.xo -k MatrixMultiplicationKernel -keep using /media/cvg/DATA/ProgramFile/SDx/2018.2/platforms/zcu102/zcu102.xpfm extracting xo v3 file /home/cvg/YJ/gemm_hls-master/build/MatrixMultiplication_hw.xo Creating IP database /home/cvg/YJ/gemm_hls-master/build/_x/link/sys_link/_sds/.cdb/xd_ip_db.xml processing accelerators: /home/cvg/YJ/gemm_hls-master/build/_x/link/sys_link/iprepo/xilinx_com_hls_MatrixMultiplicationKernel_1_0 ip_dir: /home/cvg/YJ/gemm_hls-master/build/_x/link/sys_link/iprepo/xilinx_com_hls_MatrixMultiplicationKernel_1_0 /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/xsltproc --stringparam xpath "spirit:component/spirit:name/text()" /media/cvg/DATA/ProgramFile/SDx/2018.2/scripts/xdcc/xpathValueOf.xsl /home/cvg/YJ/gemm_hls-master/build/_x/link/sys_link/iprepo/xilinx_com_hls_MatrixMultiplicationKernel_1_0/component.xml ip_name: MatrixMultiplicationKernel Creating apsys_0.xml

Creating dr.bd.tcl /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf2xd: 4: /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf2xd: [[: not found /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf2xd: 4: /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf2xd: [[: not found INFO: [CF2XD 83-2203] Adding accelerator adapters... INFO: [CF2XD 83-2200] Adding axi_interconnects... INFO: [CF2XD 83-2201] Adding axi_stream_router for scatter-gather DMAs... INFO: [CF2XD 83-2202] Adding axi_dwidth_converters... INFO: [CF2XD 83-2208] Adding bus connections for logical connections... INFO: [CF2XD 83-2205] Adding clock connections... INFO: [CF2XD 83-2206] Adding reset connections... /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf_xsd: 4: /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf_xsd: [[: not found /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf_xsd: 4: /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf_xsd: [[: not found INFO: [XOCC 60-812] xocc command line options for vpl are -t hw -f zcu102 --kernel_frequency 250 --xp param:compiler.enablePerformanceTrace=1 --xp misc:report=type report_timing_summary name impl_report_timing_summary_route_design_summary steps {route_design} runs {impl_1} options {-max_paths 10} --xp prop:kernel.MatrixMultiplicationKernel.kernel_flags= -std=c++11 -O3 -DMM_SYNTHESIS -DHLSLIB_SYNTHESIS --xp param:compiler.lockFlowCritSlackThreshold=0 --xp vivado_prop:run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED=true --xp vivado_prop:run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true --xp vivado_prop:run.KERNEL.{STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS}={-directive sdx_optimization_effort_high} --xp param:compiler.enableRunInBitstreamGeneration=1 -s

** vpl v2018.2 (64-bit) ** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 Copyright 198S6-2018 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: ap_opencl WARNING: [VPL 17-301] Failed to get a license for 'ap_opencl'. Explanation: The license feature ap_opencl could not be found. Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". Attempting to get a license: ap_sdsoc Feature available: ap_sdsoc INFO: [VPL 60-839] Read in kernel information from file '/home/cvg/YJ/gemm_hls-master/build/_x/link/int/kernel_info.dat'. INFO: [VPL 60-423] Target device: zcu102 INFO: [VPL 60-1032] Extracting DSA to /home/cvg/YJ/gemm_hls-master/build/_x/link/vivado/.local/dsa INFO: [VPL 60-251] Hardware accelerator integration... Creating Vivado project and starting FPGA synthesis. [13:35:42] Block-level synthesis in progress, 0 of 12 jobs complete, 6 jobs running. [13:36:42] Block-level synthesis in progress, 3 of 12 jobs complete, 5 jobs running. [13:37:42] Block-level synthesis in progress, 6 of 12 jobs complete, 4 jobs running. [13:38:42] Block-level synthesis in progress, 10 of 12 jobs complete, 2 jobs running. [13:39:42] Block-level synthesis in progress, 11 of 12 jobs complete, 1 job running. [13:40:42] Block-level synthesis in progress, 11 of 12 jobs complete, 1 job running. [13:41:42] Block-level synthesis in progress, 11 of 12 jobs complete, 1 job running. [13:42:42] Block-level synthesis in progress, 11 of 12 jobs complete, 1 job running. [13:43:42] Block-level synthesis in progress, 12 of 12 jobs complete, 0 jobs running. [13:44:42] Top-level synthesis in progress.

===>The following messages were generated while processing /home/cvg/YJ/gemm_hls-master/build/_x/link/vivado/prj/prj.runs/impl_1 : ERROR: [VPL-4] ERROR: [Common 17-55] 'getproperty' expects at least one object. Resolution: If [get] was used to populate the object, check to make sure this command returns at least one valid object. ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, Design Initialization ERROR ERROR: [VPL 60-806] Failed to finish platform linker ERROR: [XOCC 60-398] vpl failed ERROR: [XOCC 60-626] Kernel link failed to complete ERROR: [XOCC 60-703] Failed to finish linking CMakeFiles/link_hardware.dir/build.make:57: recipe for target 'CMakeFiles/link_hardware' failed make[3]: [CMakeFiles/link_hardware] Error 1 CMakeFiles/Makefile2:242: recipe for target 'CMakeFiles/link_hardware.dir/all' failed make[2]: [CMakeFiles/link_hardware.dir/all] Error 2 CMakeFiles/Makefile2:249: recipe for target 'CMakeFiles/link_hardware.dir/rule' failed make[1]: [CMakeFiles/link_hardware.dir/rule] Error 2 Makefile:194: recipe for target 'link_hardware' failed make: [link_hardware] Error 2

How can I solve this problem? Thanks very much.

yangjing69 commented 5 years ago

Sorry, I forget to tell you all the changes in CMakeLists.txt which is in the gemm_hls-master project:

Target options

set(MM_PART_NAME "xczu9eg-ffvb1156-2-e" CACHE STRING "Part name for HLS.") set(MM_DSA_NAME "zcu102" CACHE STRING "DSA string for xocc.") set(MM_TARGET_CLOCK 250 CACHE STRING "Target clock for kernel (<=0 uses DSA default).") set(MM_TARGET_CLOCK_UNCERTAINTY 1.08 CACHE STRING "Clock uncertainty for HLS.")

Domain options

set(MM_DATA_TYPE "float" CACHE STRING "Matrix data type.") set(MM_MEMORY_BUS_WIDTH_N 64 CACHE STRING "Width of memory bus in bytes in N.") set(MM_MEMORY_BUS_WIDTH_K 64 CACHE STRING "Width of memory bus in bytes in K.") set(MM_MEMORY_BUS_WIDTH_M 64 CACHE STRING "Width of memory bus in bytes in M.") set(MM_DYNAMIC_SIZES CACHE OFF "Use dynamic matrix dimension sizes.") set(MM_SIZE_N 1024 CACHE STRING "Size of matrix dimension.") set(MM_SIZE_K 256 CACHE STRING "Size of matrix dimension.") set(MM_SIZE_M 1024 CACHE STRING "Size of matrix dimension.") set(MM_MEMORY_TILE_SIZE_N 256 CACHE STRING "Tile size of outer memory tile in N.") set(MM_MEMORY_TILE_SIZE_M 256 CACHE STRING "Tile size of outer memory tile in M.") set(MM_PARALLELISM_N 16 CACHE STRING "Number of parallel compute in N.") set(MM_PARALLELISM_M 4 CACHE STRING "Number of parallel compute in M.") set(MM_GRANULARITY_N 1 CACHE STRING "Granularity of processing elements in N.")

definelicht commented 5 years ago

Hi @yangjing69,

As a quick tip -- instead of changing the default parameters inside CMakeLists.txt, you can change the parameters for your build either by:

  1. Call ccmake on the directory where you are building, e.g. ccmake ., and use the interactive tool.
  2. Set them while calling cmake, like so: cmake <source dir> -DMM_SIZE_K=256

As for your error, it looks like an internal Vivado error: 'get_property' expects at least one object. It suggests that it is looking for objects that don't exist in the netlist produced by SDSoC. Unfortunately I don't have access to an SoC device/license, so I cannot test this myself - I've only tried compiling for accelerators-type FPGAs (KU115, VU9P).

I found this forum post, which might be related: https://forums.xilinx.com/t5/SDAccel/Building-ERROR-VPL-17-55-set-property-expects-at-least-one/td-p/893221 Could you check the logs that the guy in this post did? Perhaps it's related to how DRAM is configured on the SoC boards. You could try commenting out the following line on 154: https://github.com/spcl/gemm_hls/blob/master/CMakeLists.txt#L154 (max memory ports) As well as commenting out the lines setting the DIMMs from on line 176-188: https://github.com/spcl/gemm_hls/blob/master/CMakeLists.txt#L176

yangjing69 commented 5 years ago

Hi,@definelicht I tried commenting out the L154 and L176-L188 line codes in CMakeList.txt, but the problem is the same as before. I checked the logs in runme.log file which in the path "../build/_x/link/vivado/prj/prj.runs/impl_1/runme.log" as below: ...... INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 388 instances were transformed. DSP48E1 => DSP48E2 (DSP_ALU, DSP_A_B_DATA, DSP_C_DATA, DSP_MULTIPLIER, DSP_M_DATA, DSP_OUTPUT, DSP_PREADD_DATA, DSP_PREADD): 320 instances RAM32M16 => RAM32M16 (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 68 instances

41 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully link_design: Time (s): cpu = 00:01:29 ; elapsed = 00:01:43 . Memory (MB): peak = 4021.840 ; gain = 2241.625 ; free physical = 6672 ; free virtual = 13332 [OPTRACE]|19570|14|/home/cvg/YJ/gemm_hls-master/build/_x/link/vivado/prj/prj.runs/impl_1/zcu102_wrapper.tcl|vivado_impl|1554952892792|END|link_design| [OPTRACE]|19570|15|/home/cvg/YJ/gemm_hls-master/build/_x/link/vivado/prj/prj.runs/impl_1/zcu102_wrapper.tcl|vivado_impl|1554952892792|START|gray box cells| [OPTRACE]|19570|16|/home/cvg/YJ/gemm_hls-master/build/_x/link/vivado/prj/prj.runs/impl_1/zcu102_wrapper.tcl|vivado_impl|1554952892792|END|gray box cells| [OPTRACE]|19570|17|/home/cvg/YJ/gemm_hls-master/build/_x/link/vivado/prj/prj.runs/impl_1/zcu102_wrapper.tcl|vivado_impl|1554952892792|START|Design Initialization: post hook| source /home/cvg/YJ/gemm_hls-master/build/_x/link/vivado/scripts/_full_init_post.tcl WARNING: [Vivado 12-508] No pins matched '/clk_wiz_0_clk_out1'. INFO: [Timing 38-35] Done setting XDC timing constraints. WARNING: [Vivado 12-1008] No clocks found for command 'get_clocks -of_objects [get_pins /clk_wiz_0_clk_out1]'. Resolution: Verify the create_clock command was called to create the clock object before it is referenced. INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. get_clocks: Time (s): cpu = 00:00:23 ; elapsed = 00:00:06 . Memory (MB): peak = 4021.840 ; gain = 0.000 ; free physical = 6356 ; free virtual = 13016 ERROR: [runtcl-1] ERROR: [Common 17-55] 'getproperty' expects at least one object. Resolution: If [get] was used to populate the object, check to make sure this command returns at least one valid object. ERROR: [Common 17-39] 'send_msg_id' failed due to earlier errors.

INFO: [Common 17-206] Exiting Vivado at Thu Apr 11 11:21:38 2019...

definelicht commented 5 years ago

@yangjing69 Could you please try the following:

yangjing69 commented 5 years ago

Hi,@definelicht I ran VERBOSE=1 make compile_hardware and VERBOSE=1 make link_hardware as below: //---------------------------------------------------------------------------------------------- %VERBOSE=1 make compile_hardware make[3]: 离开目录“/home/cvg/YJ/gemm_hls-master/build” make -f CMakeFiles/compile_hardware.dir/build.make CMakeFiles/compile_hardware.dir/build make[3]: 进入目录“/home/cvg/YJ/gemm_hls-master/build” XILINX_PATH=/home/cvg/YJ/gemm_hls-master/build /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/xocc -c -t hw -s -I/home/cvg/YJ/gemm_hls-master/include -I/home/cvg/YJ/gemm_hls-master/hlslib/include -I/home/cvg/YJ/gemm_hls-master/build --kernel MatrixMultiplicationKernel --platform zcu102 --xp prop:kernel.MatrixMultiplicationKernel.kernel_flags=" -std=c++11 -O3 -DMM_SYNTHESIS -DHLSLIB_SYNTHESIS" -O3 --kernel_frequency 250 /home/cvg/YJ/gemm_hls-master/kernel/Compute.cpp /home/cvg/YJ/gemm_hls-master/kernel/Memory.cpp -o MatrixMultiplication_hw.xo

** xocc v2018.2 (64-bit) ** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: ap_opencl WARNING: [XOCC 17-301] Failed to get a license for 'ap_opencl'. Explanation: The license feature ap_opencl could not be found. Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". Attempting to get a license: ap_sdsoc Feature available: ap_sdsoc INFO: [XOCC 60-585] Compiling for hardware target Running SDx Rule Check Server on port:44623 INFO: [XOCC 60-895] Target platform: /media/cvg/DATA/ProgramFile/SDx/2018.2/platforms/zcu102/zcu102.xpfm INFO: [XOCC 60-423] Target device: zcu102 INFO: [XOCC 60-242] Creating kernel: 'MatrixMultiplicationKernel'

===>The following messages were generated while performing high-level synthesis for kernel: MatrixMultiplicationKernel Log file:/home/cvg/YJ/gemm_hls-master/build/_x/MatrixMultiplication_hw/MatrixMultiplicationKernel/vivado_hls.log : INFO: [XOCC 204-61] Option 'relax_ii_for_timing' is enabled, will increase II to preserve clock frequency constraints. INFO: [XOCC 204-61] Pipelining loop 'ReadA_N0_ReadA_K0_ReadA_N1_ReadA_N2'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 12. INFO: [XOCC 204-61] Pipelining loop 'TransposeA_N0_TransposeA_K_L'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4. INFO: [XOCC 204-61] Pipelining loop 'ReadB_OuterTile_N_ReadB_K_ReadB_BufferB_M1'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 11. INFO: [XOCC 204-61] Pipelining loop 'ConvertWidthB_Outer_ConvertWidthB_Memory'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4. INFO: [XOCC 204-61] Pipelining loop 'FeedB_OuterTile_N_FeedB_K_FeedB_Pipeline_N_FeedB_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 4. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'InitializeABuffer_Inner_InitializeABuffer_Outer'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2. INFO: [XOCC 204-61] Pipelining loop 'Collapse_K_Pipeline_N_Pipeline_M'. INFO: [XOCC 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 21. INFO: [XOCC 204-61] Pipelining loop 'WriteC_Flattened'. INFO: [XOCC 17-14] Message 'XOCC 204-61' appears 100 times and further instances of the messages will be disabled. INFO: [XOCC 60-594] Finished kernel compilation INFO: [XOCC 60-244] Generating system estimate report... INFO: [XOCC 60-1092] Generated system estimate report: /home/cvg/YJ/gemm_hls-master/build/_x/reports/MatrixMultiplication_hw/system_estimate_MatrixMultiplication_hw.xtxt Add Instance ConvertWidthC ConvertWidthC_U0 552 Add Instance ConvertWidthB ConvertWidthB_U0 558 Add Instance ProcessingElement87 ProcessingElement87_U0 564 Add Instance ProcessingElement89 ProcessingElement89_U0 574 Add Instance ProcessingElement91 ProcessingElement91_U0 584 Add Instance ProcessingElement88 ProcessingElement88_U0 594 Add Instance ProcessingElement90 ProcessingElement90_U0 604 Add Instance ProcessingElement92 ProcessingElement92_U0 614 Add Instance ProcessingElement93 ProcessingElement93_U0 624 Add Instance ProcessingElement94 ProcessingElement94_U0 634 Add Instance ProcessingElement95 ProcessingElement95_U0 644 Add Instance ProcessingElement96 ProcessingElement96_U0 654 Add Instance ProcessingElement97 ProcessingElement97_U0 664 Add Instance ProcessingElement98 ProcessingElement98_U0 674 Add Instance ProcessingElement99 ProcessingElement99_U0 684 Add Instance ProcessingElement100 ProcessingElement100_U0 694 Add Instance ProcessingElement101 ProcessingElement101_U0 704 Add Instance ProcessingElement102 ProcessingElement102_U0 714 Add Instance ReadA ReadA_U0 721 Add Instance WriteC WriteC_U0 744 Add Instance ReadB ReadB_U0 752 Add Instance TransposeA TransposeA_U0 760 Add Instance FeedB FeedB_U0 781 Add Instance MatrixMultiplicationKernel_entry6 MatrixMultiplicationKernel_entry6_U0 787 INFO: [XOCC 60-586] Created MatrixMultiplication_hw.xo INFO: [XOCC 60-791] Total elapsed time: 0h 1m 20s make[3]: 离开目录“/home/cvg/YJ/gemm_hls-master/build” Built target compile_hardware make[2]: 离开目录“/home/cvg/YJ/gemm_hls-master/build” /media/cvg/DATA/ProgramFile/SDK/2018.2/tps/lnx64/cmake-3.3.2/bin/cmake -E cmake_progress_start /home/cvg/YJ/gemm_hls-master/build/CMakeFiles 0 make[1]: 离开目录“/home/cvg/YJ/gemm_hls-master/build” //---------------------------------------------------------------------------------------------- %VERBOSE=1 make link_hardware /media/cvg/DATA/ProgramFile/SDK/2018.2/tps/lnx64/cmake-3.3.2/bin/cmake -H/home/cvg/YJ/gemm_hls-master -B/home/cvg/YJ/gemm_hls-master/build --check-build-system CMakeFiles/Makefile.cmake 0 make -f CMakeFiles/Makefile2 link_hardware make[1]: 进入目录“/home/cvg/YJ/gemm_hls-master/build” /media/cvg/DATA/ProgramFile/SDK/2018.2/tps/lnx64/cmake-3.3.2/bin/cmake -H/home/cvg/YJ/gemm_hls-master -B/home/cvg/YJ/gemm_hls-master/build --check-build-system CMakeFiles/Makefile.cmake 0 /media/cvg/DATA/ProgramFile/SDK/2018.2/tps/lnx64/cmake-3.3.2/bin/cmake -E cmake_progress_start /home/cvg/YJ/gemm_hls-master/build/CMakeFiles 0 make -f CMakeFiles/Makefile2 CMakeFiles/link_hardware.dir/all make[2]: 进入目录“/home/cvg/YJ/gemm_hls-master/build” make -f CMakeFiles/link_hardware.dir/build.make CMakeFiles/link_hardware.dir/depend make[3]: 进入目录“/home/cvg/YJ/gemm_hls-master/build” cd /home/cvg/YJ/gemm_hls-master/build && /media/cvg/DATA/ProgramFile/SDK/2018.2/tps/lnx64/cmake-3.3.2/bin/cmake -E cmake_depends "Unix Makefiles" /home/cvg/YJ/gemm_hls-master /home/cvg/YJ/gemm_hls-master /home/cvg/YJ/gemm_hls-master/build /home/cvg/YJ/gemm_hls-master/build /home/cvg/YJ/gemm_hls-master/build/CMakeFiles/link_hardware.dir/DependInfo.cmake --color= Dependee "/home/cvg/YJ/gemm_hls-master/build/CMakeFiles/link_hardware.dir/DependInfo.cmake" is newer than depender "/home/cvg/YJ/gemm_hls-master/build/CMakeFiles/link_hardware.dir/depend.internal". Dependee "/home/cvg/YJ/gemm_hls-master/build/CMakeFiles/CMakeDirectoryInformation.cmake" is newer than depender "/home/cvg/YJ/gemm_hls-master/build/CMakeFiles/link_hardware.dir/depend.internal". Scanning dependencies of target link_hardware make[3]: 离开目录“/home/cvg/YJ/gemm_hls-master/build” make -f CMakeFiles/link_hardware.dir/build.make CMakeFiles/link_hardware.dir/build make[3]: 进入目录“/home/cvg/YJ/gemm_hls-master/build” XILINX_PATH=/home/cvg/YJ/gemm_hls-master/build /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/xocc -l -t hw -s -I/home/cvg/YJ/gemm_hls-master/include -I/home/cvg/YJ/gemm_hls-master/hlslib/include -I/home/cvg/YJ/gemm_hls-master/build --kernel MatrixMultiplicationKernel --platform zcu102 --xp prop:kernel.MatrixMultiplicationKernel.kernel_flags=" -std=c++11 -O3 -DMM_SYNTHESIS -DHLSLIB_SYNTHESIS" -O3 --kernel_frequency 250 MatrixMultiplication_hw.xo -o MatrixMultiplication_hw.xclbin

** xocc v2018.2 (64-bit) ** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

INFO: [XOCC 60-629] Linking for hardware target Running SDx Rule Check Server on port:33665 INFO: [XOCC 60-895] Target platform: /media/cvg/DATA/ProgramFile/SDx/2018.2/platforms/zcu102/zcu102.xpfm INFO: [XOCC 60-423] Target device: zcu102 WARNING: [XOCC 60-887] No System Configuration (--sys_config) option was specified for XOCC Link. A system boot image will not be generated. The current Platform has the following System Configurations: 'a53_linux', 'a53_standalone', 'ocl', 'r5_standalone' INFO: [XOCC 60-825] xocc command line options for sdx_link are --xo MatrixMultiplication_hw.xo -k MatrixMultiplicationKernel -keep using /media/cvg/DATA/ProgramFile/SDx/2018.2/platforms/zcu102/zcu102.xpfm extracting xo v3 file /home/cvg/YJ/gemm_hls-master/build/MatrixMultiplication_hw.xo Creating IP database /home/cvg/YJ/gemm_hls-master/build/_x/link/sys_link/_sds/.cdb/xd_ip_db.xml processing accelerators: /home/cvg/YJ/gemm_hls-master/build/_x/link/sys_link/iprepo/xilinx_com_hls_MatrixMultiplicationKernel_1_0 ip_dir: /home/cvg/YJ/gemm_hls-master/build/_x/link/sys_link/iprepo/xilinx_com_hls_MatrixMultiplicationKernel_1_0 /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/xsltproc --stringparam xpath "spirit:component/spirit:name/text()" /media/cvg/DATA/ProgramFile/SDx/2018.2/scripts/xdcc/xpathValueOf.xsl /home/cvg/YJ/gemm_hls-master/build/_x/link/sys_link/iprepo/xilinx_com_hls_MatrixMultiplicationKernel_1_0/component.xml ip_name: MatrixMultiplicationKernel Creating apsys_0.xml

Creating dr.bd.tcl /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf2xd: 4: /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf2xd: [[: not found /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf2xd: 4: /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf2xd: [[: not found INFO: [CF2XD 83-2203] Adding accelerator adapters... INFO: [CF2XD 83-2200] Adding axi_interconnects... INFO: [CF2XD 83-2201] Adding axi_stream_router for scatter-gather DMAs... INFO: [CF2XD 83-2202] Adding axi_dwidth_converters... INFO: [CF2XD 83-2208] Adding bus connections for logical connections... INFO: [CF2XD 83-2205] Adding clock connections... INFO: [CF2XD 83-2206] Adding reset connections... /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf_xsd: 4: /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf_xsd: [[: not found /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf_xsd: 4: /media/cvg/DATA/ProgramFile/SDx/2018.2/bin/cf_xsd: [[: not found INFO: [XOCC 60-812] xocc command line options for vpl are -t hw -f zcu102 --kernel_frequency 250 --xp param:compiler.enablePerformanceTrace=1 --xp misc:report=type report_timing_summary name impl_report_timing_summary_route_design_summary steps {route_design} runs {impl_1} options {-max_paths 10} --xp prop:kernel.MatrixMultiplicationKernel.kernel_flags= -std=c++11 -O3 -DMM_SYNTHESIS -DHLSLIB_SYNTHESIS --xp param:compiler.lockFlowCritSlackThreshold=0 --xp vivado_prop:run.impl_1.STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED=true --xp vivado_prop:run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=true --xp vivado_prop:run.KERNEL.{STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS}={-directive sdx_optimization_effort_high} --xp param:compiler.enableRunInBitstreamGeneration=1 -s

** vpl v2018.2 (64-bit) ** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018 Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: ap_opencl WARNING: [VPL 17-301] Failed to get a license for 'ap_opencl'. Explanation: The license feature ap_opencl could not be found. Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". Attempting to get a license: ap_sdsoc Feature available: ap_sdsoc INFO: [VPL 60-839] Read in kernel information from file '/home/cvg/YJ/gemm_hls-master/build/_x/link/int/kernel_info.dat'. INFO: [VPL 60-423] Target device: zcu102 INFO: [VPL 60-1032] Extracting DSA to /home/cvg/YJ/gemm_hls-master/build/_x/link/vivado/.local/dsa INFO: [VPL 60-251] Hardware accelerator integration... Creating Vivado project and starting FPGA synthesis. [10:36:26] Block-level synthesis in progress, 0 of 12 jobs complete, 6 jobs running. [10:37:26] Block-level synthesis in progress, 5 of 12 jobs complete, 5 jobs running. [10:38:26] Block-level synthesis in progress, 8 of 12 jobs complete, 2 jobs running. [10:39:26] Block-level synthesis in progress, 11 of 12 jobs complete, 1 job running. [10:40:26] Block-level synthesis in progress, 11 of 12 jobs complete, 1 job running. [10:41:26] Block-level synthesis in progress, 11 of 12 jobs complete, 1 job running. [10:42:26] Block-level synthesis in progress, 11 of 12 jobs complete, 1 job running. [10:43:26] Block-level synthesis in progress, 11 of 12 jobs complete, 1 job running. [10:44:26] Block-level synthesis in progress, 11 of 12 jobs complete, 1 job running. [10:45:26] Block-level synthesis in progress, 11 of 12 jobs complete, 1 job running. [10:46:26] Top-level synthesis in progress.

===>The following messages were generated while processing /home/cvg/YJ/gemm_hls-master/build/_x/link/vivado/prj/prj.runs/impl_1 : ERROR: [VPL-4] ERROR: [Common 17-55] 'getproperty' expects at least one object. Resolution: If [get] was used to populate the object, check to make sure this command returns at least one valid object. ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, Design Initialization ERROR ERROR: [VPL 60-806] Failed to finish platform linker ERROR: [XOCC 60-398] vpl failed ERROR: [XOCC 60-626] Kernel link failed to complete ERROR: [XOCC 60-703] Failed to finish linking CMakeFiles/link_hardware.dir/build.make:57: recipe for target 'CMakeFiles/link_hardware' failed make[3]: [CMakeFiles/link_hardware] Error 1 make[3]: 离开目录“/home/cvg/YJ/gemm_hls-master/build” CMakeFiles/Makefile2:242: recipe for target 'CMakeFiles/link_hardware.dir/all' failed make[2]: [CMakeFiles/link_hardware.dir/all] Error 2 make[2]: 离开目录“/home/cvg/YJ/gemm_hls-master/build” CMakeFiles/Makefile2:249: recipe for target 'CMakeFiles/link_hardware.dir/rule' failed make[1]: [CMakeFiles/link_hardware.dir/rule] Error 2 make[1]: 离开目录“/home/cvg/YJ/gemm_hls-master/build” Makefile:194: recipe for target 'link_hardware' failed make: [link_hardware] Error 2

definelicht commented 5 years ago

Sorry, I don't have experience compiling for SoC devices.

WARNING: [XOCC 60-887] No System Configuration (--sys_config) option was specified for XOCC Link. A system boot image will not be generated. The current Platform has the following System Configurations: 'a53_linux', 'a53_standalone', 'ocl', 'r5_standalone'

Could this be an issue? Have you tried building other OpenCL kernels for your platform? Could you check what flags are set for those builds?

definelicht commented 4 years ago

Closing due to inactivity. Feel free to reopen with new information.