correct DRC violations

[proppy]

The precheck jobs came up with the following failure:

{{FAILURE}} 3 Check(s) Failed: ['Klayout FEOL', 'Klayout BEOL', 'Klayout Offgrid'] !!!

See the logs on https://github.com/proppy/caravel_user_project/actions/runs/4264589409/jobs/7422863825

Attached the violation db for FEOL and BEOL (the offgrid is too big: 4go!) klayout_precheck.zip

But you can access the full precheck-results artefact from the actions summary: https://github.com/proppy/caravel_user_project/actions/runs/4264589409

[njcoburn]

If I run DRC on sections of the design (by deleting other areas) I do not get significant DRC errors. Only metal/poly fills & off-grid warnings. The only significant DRC error for the PFETS is the min/max Via1 size - as shown here....

[njcoburn]

I did the same for the nfets (with the large central transistors deleted - as the DRC check takes hours to run when they are present).

Same sort of errors - off grid is the main culprit as this design is at 0.001.

If you @proppy can change this at the global level to 0.005 - I believe that this will take care of the 100,000+ DRC errors.

[proppy]

Managed to run the DRC on the whole macro by removing the antenna and density checks, see the report below: gf180_drc.zip

[njcoburn]

@proppy How do you remove the antenna & density checks?

[proppy]

rebuilding a new version of the installer here https://github.com/proppy/conda-eda/actions/runs/4265736470 without density and antenna checks, it should be baked and show up under https://github.com/proppy/conda-eda/releases in ~30min.

[proppy]

@proppy How do you remove the antenna & density checks?

deleted them in the gf180mcu.drc file, attached a copy here: gf180_drc.zip

[njcoburn]

I did a full DRC check on the design - after editing V1 to get around some of those errors (successfully!).

Discounting the OFFGRID errors - we now only have a limitied number of errors.

V4.1 has 13428 errors - these are coming from the capacitors that were supplied to us.

[njcoburn]

Changing all VIAS to 0.26 microns square on all layers resolved the DRC errors seen previously. Now only OFFGRID errors remain.

[njcoburn]

@proppy is OFFGRID resolvable somehow? Also - is it a real concern for tapeout? Will the fab reject the design if there is an OFFGRID error?

[proppy]

OFFGRID resolvable somehow

Did you try to copy the existing design on top of a new layout with a 0.005 grid? I'd expect some hand tweaking to be necessary but maybe that can give you a way to kickstart the effort?

is it a real concern for tapeout

The rule is part of the design manual, see https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_07_02.html#design-geometry-rules and enabled by default in the rules deck, see https://github.com/efabless/globalfoundries-pdk-libs-gf180mcu_fd_pr/tree/main/rules/klayout/drc#switchesso

So it seems important ;)

Will the fab reject the design if there is an OFFGRID error?

The fab will reject any design with DRC errors per https://gf180mcu-pdk.readthedocs.io/en/latest/physical_verification/design_manual/drm_06.html unless a waiver is provided for each failure instance.

A quick search reveal that grid alignement might be relevant during mask manufacturing (so that they know where it's safe to divide tiles?).

[proppy]

Also got two DRC errors from magic on the combined Top_level_oscillator macro + and gate:

----------------------------------------
Both LV and MV devices cannot be in the same N-well (DV.9)
----------------------------------------
 74.330um 133.525um 129.630um 160.000um
 159.330um 133.525um 160.000um 160.000um
----------------------------------------

And the following DRC errors from klayout on the standalone Top_level_oscillator macro:

[njcoburn]

These errors that you have - 3,354,302. These appear to be coming from the fills that are auto generated. Waiting to verify on my end...

[proppy]

Note that the klayout DRC were running on the oscillator analog macro before it gets thru OpenLane.

[njcoburn]

Getting closer.... changed grid to 0.005 and realigned a lot of vias manually. Other issues have appeared but seem to be resolvable manually. These issues arose due to changing the grid to 0.001 [the reason being (if I remember correctly) to pass LVS at the time before a certain fix].