Audio PCM to PDM conversion

[sporniket]

Run the process at f(PDM) >> f(PCM)

At each step N

When

• the PCM input is X(N)
• Error(N-1) = the quantization error of step(N-1) or 0 when N < 1
• Error(N-2) = the quantization error of step(N-2) or 0 when N < 2
• Error(N-3) = the quantization error of step(N-3) or 0 when N < 3

Then

• The value to quantize X'(N) = X(N) + int(0.6Error(N-1)) + int(0.16Error(N-2)) + int(0.06*Error(N-3))
• The quantized value Q(N) = (X'(N) < 128) ? 0 : 255
• The quantization error Error(N) = X'(N) - Q(N)

Notes

• The contribution of Error(N-2) as E = 0,4 (E - 0.6 E) = 0.4 (1 - 0.6) E = 0.4 0.4 E = 0.16 * E
• The contribution of Error(N-3) as E = 0,25 (E - 0.6 E - 0.16 E) = 0.25 (1 - 0.76) E = 0.25 0.24 E = 0.06 E
• Only (0.6 + 0.16 + 0.06) E = 0.82 E of the quantization error is fed back. 18% of the error is lost.

[sporniket]

binary approximation :

Target Computation	Binary Approximation
0.6x	x - x>>2 - x>>3 - x>>5
0.16x	x>>3 + x>>5 + x>>8
0.06x	x>>4 - x>>9

[powerpun]

how about using FPGA to implement this?

[sporniket]

That's the plan

[powerpun]

there was a verilog there already: https://github.com/AUDIY/FPGA_PCM2DSD

[powerpun]

but I don't know how to evaluate the code's result for THD/group delay in an easy way.

[sporniket]

Thanks for the pointer, however it seems to be about doing the reverse (PDM to PCM) of what I want (PCM to PDM)

No idea about the THD.

This is for a core generating sound signal as PCM, and converting to PDM to use a single GPIO pin plugged to a speaker (with suitable circuitry)

[powerpun]

the verilog code I link is the PCM to DSD(PDM), not the reverse. please check the comment, which the input is PCM I2S output is DSD(PDM)

• Description
• Input
• BCLK_I : I2S Bit Clock Input
• LRCK_I : I2S L/R Clock Input
• DATA_I : I2S DATA Input
• RST_I : Reset (Active Low)
• Output
• BCLK_O : I2S Bit Clock Output (Through BCLK_I)
• WCLK_O : Parallel PCM Word Clock Output
• DATAL_O: Parallel PCM Left Data Output
• DATAR_O: Parallel PCM Right Data Output

[sporniket]

yes, don't mind my previous comment not being what I want (I stroked it minutes after posting, when I had a better look).

Anyway thanks.

[powerpun]

it's fine. so what you wanna do? I wanna build this an ASIC but still need to evaluate this first in FPGA, I need help. I have some patents in audio playback. also low latency BT audio. (5ms)

[sporniket]

Then I think that I am not the right person for your project. This ticket is just a written down idea for a personnal, hobbyist-ish and opensource project with no commercial prospect whatsoever. And the expected time of beginning this part is undetermined -provided I need this part at all-.

I wish you good luck :)

[powerpun]

it's ok, and I got the C++ code for the conversation. so that I could translate c++ to verilog