Open sporniket opened 2 years ago
binary approximation :
Target Computation | Binary Approximation |
---|---|
0.6x | x - x>>2 - x>>3 - x>>5 |
0.16x | x>>3 + x>>5 + x>>8 |
0.06x | x>>4 - x>>9 |
how about using FPGA to implement this?
That's the plan
there was a verilog there already: https://github.com/AUDIY/FPGA_PCM2DSD
but I don't know how to evaluate the code's result for THD/group delay in an easy way.
Thanks for the pointer, however it seems to be about doing the reverse (PDM to PCM) of what I want (PCM to PDM)
No idea about the THD.
This is for a core generating sound signal as PCM, and converting to PDM to use a single GPIO pin plugged to a speaker (with suitable circuitry)
the verilog code I link is the PCM to DSD(PDM), not the reverse. please check the comment, which the input is PCM I2S output is DSD(PDM)
yes, don't mind my previous comment not being what I want (I stroked it minutes after posting, when I had a better look).
Anyway thanks.
it's fine. so what you wanna do? I wanna build this an ASIC but still need to evaluate this first in FPGA, I need help. I have some patents in audio playback. also low latency BT audio. (5ms)
Then I think that I am not the right person for your project. This ticket is just a written down idea for a personnal, hobbyist-ish and opensource project with no commercial prospect whatsoever. And the expected time of beginning this part is undetermined -provided I need this part at all-.
I wish you good luck :)
it's ok, and I got the C++ code for the conversation. so that I could translate c++ to verilog
At each step N
When
Then
Notes