a simulated Bus driver to communicate with external peripheral (data, address, controls). Job completion takes at least N microcore cycles to complete, N ≥ 4.
a decoder, for now everything decodes into NOP.
a register file, containing only the Program Counter (PC)
a microcore ROM that contains the microcore program
a microcore with an internal PC
an address ALU ADALU
steps
Power on
The register’s PC is zeroed, as well as the internal PC.
Main loop
the register file expose the PC towards the Bus driver and the address ALU as first operand
the immediate value 2 is exposed to the address ALU as second operand
the operation of the address ALU is set to ADD
the address ALU output is exposed toward the register file into the PC
the microcore wait for the Bus driver to be ready
the bus driver expose data fetched toward the decoder
the decoder expose the new internal PC toward the microcore
Pseudo micro code
start:
move.l reg(PC),Bus(1)|ADALU(1) ;Bus(1) = address + execute on write ; ADALU(1) = first operand
move.l #2,ADALU(2) ; ADALU(2) = second operand
move.l #ADD,ADALU(3) ; ADALU(3) = operation + execute on write
move.l ADALU(0),reg(PC) ; ADALU(0) = result
wait Bus
move.l Bus(0), Decoder(1) ; Bus(0) = data fetched ; Decoder(1) = opcode
wait Decoder
jmp Decoder(0) ; Decoder(0) = micro-rom address, returns 0
Let a fictitious CPU having :
PC
)ADALU
steps
Power on
The register’s PC is zeroed, as well as the internal PC.
Main loop
Pseudo micro code