Open sporniket opened 2 weeks ago
On reading a little the yosys manual about technological mapping, and seeing an exemple that should work there : https://github.com/hoglet67/atf15xx_yosys
See how to generate a liberty file descriptor.
More about liberty file format :
3 logic diagrams using fuse liste [SYN,AC0] : Registered (01), Complex (11), Simple(01)
fuse list in ascending order
products: starts at 0, 8 rows of 32 fuses per macro cells = 256 fuses per macro cells = 2048 Interconnect switches UIM1
~UIM2048
MC1:0000~0255
MC2:0256~0511
MC3:0512~0767
MC4:0768~1023
MC5:1024~1279
MC6:1280~1535
MC7:1536~1791
MC8:1792~2047
XOR fuse, one per MC
MC1.XOR = 2048
...
MC8.XOR = 2055
64 user electronic signature fuses, from MSB to LSB
User[63]:2056
...
User[0]:2119
AC1 fuse, one per MC
MC1.AC1 = 2120
...
MC8.AC1 = 2127
PTD (Product Term Disable) fuses, one per row of products (= 64 fuses)
MC1.PTD1~MC1.PTD8:2128~2135
MC2.PTD1~MC2.PTD8:2136~2143
MC3.PTD1~MC3.PTD8:2144~2151
MC4.PTD1~MC4.PTD8:2152~2159
MC5.PTD1~MC5.PTD8:2160~2167
MC6.PTD1~MC6.PTD8:2168~2175
MC7.PTD1~MC7.PTD8:2176~2183
MC8.PTD1~MC8.PTD8:2184~2191
Global fuses :
SYN:2192
AC0:2193
TOTAL : 2194 fuses = 16×137 + 2
Sample JED file for a GAL16V8 source
Used Program: GALasm 2.0
GAL-Assembler: GALasm 2.0
Device: GAL16V8
*F0
*G0
*QF2194
*L0000 11101111111111111111111111111111
*L0032 01111111111111111111111111111111
*L0256 11111111111111111111111111111111
*L0288 11110111111111111111111111111111
*L0320 11111111011111111111111111111111
*L0512 11111111111101110111111111111111
*L0544 11111111111111111111101111111111
*L2048 11100000
*L2056 0100010101111000011000010010111000110010000000000000000000000000
*L2120 11100000
*L2128 1111111111111111111111111111111111111111111111111111111111111111
*L2192 1
*L2193 1
*C25a8
*
7305
draft overview of the json database :
{
"GAL16V8_Registered":{
"pins":{
"DIP20":{
# pad naming
# special names : C1, E1 (from prjbureau) for Clock and Output Enable, respectively (registered mode)
# Input pad names : I1~I10 (**NEW**) for input pins (I1 instead of C1, I10 instead of E1 in complex/simple mode)
# I/O/Q names : M1~M8 (from prjbureau), Mx is tied to MCx
"C1": 1, # pin 1 is Clock --> special pad C1
"I2": 2,
#...
"I9": 9,
"E1": 11, # pin 11 is Output Enable --> special pad E1
"M8": 12, # pin 12 to
#...
"M1": 19,
},
"PLCC20":{}
},
"specials":{
# (**NEW**) Using the special function name 'CLK' and 'OE' as named by the datasheet
"CLK":"C1",
"OE":"E1"
},
"blocks":{
# There is only one block
"A":{
"macrocells":[
"MC1",
#...
"MC8"
],
"switches":[
# provisionnal : each of the 64 rows of 32 fuses 0~2047 ?
"UIM1",
#...
"UIM63"
],
"pterm_points":{
### HERE ###
# The 2048 fuses of the matrix ?
"UIM1_1": 0,
"UIM1_2": 1,
# ...
"UIM1_30": 30,
"UIM1_31": 31,
"UIM2_1": 32,
"UIM2_2": 33,
# ...
"UIM63_30": 2046,
"UIM63_31": 2047,
},
}
},
"macrocells":{
"MC1":{
"block": "A",
"pad": "M1",
"pterm_ranges":{
"PT1":[0,32],
"PT2":[32,64],
# ...
"PT8":[224,256]
},
"pterm_disables":{
# (**NEW**) Map product term to product term disable fuse
# 2128~2135
# Provisionnal -- otherwise, each PTD is a configuration of the cell ??
"PTD1":2128,
#...
"PTD8":2135,
},
"configuration":{ # AC1 fuse
"fuses":[2120],
"values":{
"registered":0,
"combinatorial":1
}
},
"polarity":{ # XOR fuse
"fuses":[2048],
"values":{
"active low":0,
"active high":1
}
},
},
# ...
"MC8":{}
},
"switches":{
"UIM1": {
"block": "A",
"mux": {
"fuses": [
0,
# ...
,31
],
},
# ...
"UIM63": {
"block": "A",
"mux": {
"fuses": [
2016,
# ...
,2047
],
},
},
},
"globals":{
"mode":{ # AC1 fuse
"fuses":[2192, 2193], # SYN, AC0
"values":{
"registered":2,
#"complex":3,
#"simple":1
}
},
}
},
# ...
"GAL16V8_Complex":{
"globals":{
"mode":{ # AC1 fuse
"fuses":[2192, 2193], # SYN, AC0
"values":{
#"registered":2,
"complex":3,
#"simple":1
}
},
}
},
"GAL16V8_Registered":{
"globals":{
"mode":{ # AC1 fuse
"fuses":[2192, 2193], # SYN, AC0
"values":{
#"registered":2,
#"complex":3,
"simple":1
}
},
}
},
}
This idea is now hosted there : prjtabouret
prjbureau
Goal
get a single chip database file containing a machine-readable description of every known fuse.
Roadmap